Design and Development of A Modified AXI Based BIST Technique for Memory Architectures
K.V.B.V Rayudu1, D R Jahagirdar2, P Srihari Rao3
1K.V.B.V Rayudu, Scientist „G‟ Head, Reliability Engineering Division, Research Centre Imarat, Vignyanakancha Po, Hyderabad, India.
2D R Jahagirdar, Scientist „G‟ Research Centre Imarat, Vignyana Kancha Po, Hyderabad, India.
3Dr P Srihari Rao, Associate Professor, NIT Warangal, Telangana, India.
Manuscript received on November 12, 2019. | Revised Manuscript received on November 23, 2019. | Manuscript published on 30 November, 2019. | PP: 8023-8029 | Volume-8 Issue-4, November 2019. | Retrieval Number: D4446118419/2019©BEIESP | DOI: 10.35940/ijrte.D4446.118419
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Memory testing and fault detection is an important phase in testing the hardware devices. This improves the overall performance of the system and prevents runtime failures in the devices. Built In Self Test (BIST) is a hardware memory test architecture deployed in many System on Chip devices to enable fault detection. This technique reduces the cost and time needed to test the memory systems. Different BIST modules need to be used to detect faults in different memories. As a result, design complexity increases. In order to overcome these above shortcomings, it is essential to develop advanced extensible Interface (AXI) with Block Random Access Memory (BRAM) and Design and Develop AXI based self-test memory architecture (March Algorithms) to achieve parallel read and write capability. The proposed model reduced the dynamic power and the clock cycles needed for simulation when compared to existing techniques.
Keywords: As A Result, Design Complexity Increases.
Scope of the Article: Analysis of Algorithms and Computational Complexity.