Design of Fin FET based 128 bit SRAM in 7nm & Various Effects near Threshold Operation for Ultra Low Power Application
T. Vasudeva Reddy1, K. Madhava Rao2, P. Kavitha Reddy3
1T. Vasudeva Reddy*, Associate Professor, Department of ECE, B. V. Raju Institute of Technology, Narsapur, Medak (dt), Telangana, India.
2K. Madhava Rao, Assistant Professor, Department of ECE, B. V. Raju Institute of Technology, Narsapur, Medak (dt), Telangana, India.
3P. Kavitha Reddy, Associate Professor, Department of ECE, B. V. Raju Institute of Technology, Narsapur, Medak (dt), Telangana, India.

Manuscript received on January 01, 2020. | Revised Manuscript received on January 20, 2020. | Manuscript published on January 30, 2020. | PP: 3361-3366 | Volume-8 Issue-5, January 2020. | Retrieval Number: E5870018520/2020©BEIESP | DOI: 10.35940/ijrte.E5870.018520

Open Access | Ethics and Policies | Cite | Mendeley
© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: With the existing technology and survey it indicates the increasing the number of transistors count and exploring methodologies leads to innovative design in memories. In general SRAM occupies considerable amount of area and less performance due to leakage power that limits the operation under sub threshold region. The power consumption of the circuit design is primarily depends on the switching activity of the transistor that leads to increasing of leakage current at near or subthreshold operation. Some of the challenges like PVT variations, SEU, SEE, and RDF lead to reduction in performance, increasing the power, BTI, sizing, delay and yield. The research work in this paper primarily describes the challenges with the technology and effects on CMOS & Finfet designs. The second aspect of the paper is to represents the design methodologies of CMOS & FinFET models and its operation. The third part of the paper explains design tradeoff of FinFET SRAM. Final sections present a comparison of high performance, low power at normal and near threshold operation. The Comparisons is made on the basis of process parameters and made a conclusion with circuit functionality, reliability under different technologies. FinFET based SRAM’s are the emerging memory trends by the performance under or near sub-threshold operation with the minimal variation in the leakage current, minimal gate delay is an alternate solution to the traditional CMOS memory designs as showed in the present work.
Keywords: SEU, SEE, RDF, BTI, LET, RSNM, WSNM, FINFET, PR, PU.
Scope of the Article: Learning Software Design Engineering.