Abstract
A system organised as a Hierarchy of Processor-And-Memory (HPAM) extends the familiar notion of memory hierarchy by including processors with different performance in different levels of the hierarchy. Tasks are assigned to different hierarchy levels according to their degree of parallelism. This paper studies the spatial locality (with respect to degree of parallelism) behaviour of simulated parallelised benchmarks in multi-level HPAM systems, and presents an inter-level cache coherence protocol that supports inclusion and multiple block sizes on an HPAM architecture. Inter-level miss rates and traffic simulation results show that the use of multiple data transfer sizes (as opposed to a unique size) across the HPAM hierarchy allows the reduction of data traffic between the uppermost levels in the hierarchy while not degrading the miss rate in the lowest level.
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Figueiredo, R.J.O., Fortes, J.A.B., Miled, Z.B. (1999). Spatial Data Locality with Respect to Degree of Parallelism in Processor-and-Memory Hierarchies. In: Hernández, V., Palma, J.M.L.M., Dongarra, J.J. (eds) Vector and Parallel Processing – VECPAR’98. VECPAR 1998. Lecture Notes in Computer Science, vol 1573. Springer, Berlin, Heidelberg. https://doi.org/10.1007/10703040_30
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DOI: https://doi.org/10.1007/10703040_30
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