Abstract
Dynamic voltage scaling (DVS) allows a program to execute at a non-peak CPU frequency in order to reduce CPU power, and hence, energy consumption; however, it is oftentimes done at the expense of performance degradation. For a program whose execution time is bounded by peripherals’ performance rather than the CPU speed, applying DVS to the program will result in negligible performance penalty. Unfortunately, existing DVS-based power-management algorithms are conservative in the sense that they overly exaggerate the impact that the CPU speed has on the execution time. We propose a new DVS algorithm that detects the CPU-boundedness of a program on the fly (via a regression method on the past MIPS rate) and then adjusts the CPU frequency accordingly. To illustrate its effectiveness, we compare our algorithm with other DVS algorithms on real systems via physical measurements.
Available as technical report LA-UR-04-7195.
An erratum to this chapter can be found at http://dx.doi.org/10.1007/11574859_13 .
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References
Lorch, J., Smith, A.: Improving dynamic voltage algorithms with PACE. In: International Conference on Measurement and Modeling of Computer Systems (June 2001)
Miyoshi, A., Lefurgy, C., Hensbergen, E., Rajkumar, R.: Critical power slope: Understanding the runtime effects of frequency scaling. In: International Conference on Supercomputing (June 2002)
Kim, W., Kim, J., Min, S.: Preemption-aware dynamic voltage scaling in hard real-time systems. In: International Symposium on Low Power Electronics and Design (August 2004)
Hsu, C.-H., Kremer, U.: The design, implementation, and evaluation of a compiler algorithm for CPU energy reduction. In: ACM SIGPLAN Conference on Programming Languages Design and Implementation (June 2003)
Li, H., Cher, C.-Y., Vijaykumar, T., Roy, K.: VSV: L2-miss-driven variable supply-voltage scaling for low power. In: International Symposium on Microarchitecture (December 2003)
Choi, K., Soma, R., Pedram, M.: Fine-grained dynamic voltage and frequency scaling for precise energy and performance trade-off based on the ration of off-chip access to on-chip computation time. In: Design Automation and Test in Europe Conference (February 2004)
Choi, K., Soma, R., Pedram, M.: Dynamic voltage and frequency scaling based on workload decomposition. In: International Symposium on Low Power Electronics and Design (August 2004)
Yao, F., Demers, A., Shenker, S.: A scheduling model for reduced cpu energy. In: IEEE Annual Symposium on Foundations of Computer Science (October 1995)
Ishihara, T., Yasuura, H.: Voltage scheduling problem for dynamically variable voltage processors. In: International Symposium on Low Power Electronics and Design (August 1998)
Seth, K., Anantaraman, A., Mueller, F., Rotenberg, E.: FAST: Frequency-aware static timing analysis. In: International Real-Time Systems Symposium (December 2003)
Hsu, C.-H., Kremer, U., Hsiao, M.: Compiler-directed dynamic frequency and voltage scheduling. In: Workshop on Power-Aware Computer Systems (November 2000)
Cormen, T.H., Leiserson, C.E., Rivest, R.L.: Introduction to Algorithms. MIT Press, Cambridge (1990)
Hirofumi, N., Naoya, N., Katsuya, T.: WT210/WT230 digital power meters. Yokogawa Technical Report 35 (2003)
The Standard Performance Evaluation Corporation, http://www.spec.org
Sun Fire B100x Blade Server, http://www.sun.com/servers/entry/b100x/
Grunwald, D., Levis, P., Farkas, K., Morrey III, C., Neufeld, M.: Policies for dynamic clock scheduling. In: Symposium on Operating System Design and Implementation (October 2000)
Varma, A., Ganesh, B., Sen, M., Choudhary, S., Srinivasan, L., Jacob, B.: A control-theoretic approach to dynamic voltage scaling. In: International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (October 2003)
AbouGhazaleh, N., Mossé, D., Childers, B., Melhem, R.: Toward the placement of power management points in real time applications. In: Workshop on Compilers and Operating Systems for Low Power (September 2001)
Azevedo, A., Issenin, I., Cornea, R., Gupta, R., Dutt, N., Veidenbaum, A., Nicolau, A.: Profile-based dynamic voltage scheduling using program checkpoints in the COPPER framework. In: Design Automation and Test in Europe Conference (March 2002)
Childers, B., Tang, H., Melhem, R.: Adapting processor supply voltage to instruction-level parallelism. In: Kool Chips Workshop (December 2000)
Hsu, C.-H.: Compiler-Directed Dynamic Voltage and Frequency Scaling for CPU Power and Energy Reduction. PhD thesis, Department of Computer Science, Rutgers University, New Brunswick, New Jersey (June 2003)
AbouGhazaleh, N., Mossé, D., Childers, B., Melhem, R., Craven, M.: Collaborative operating system and compiler power management for real-time applications. In: Real-Time Embedded Technology and Applications Symposium (May 2003)
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Hsu, CH., Feng, WC. (2005). Effective Dynamic Voltage Scaling Through CPU-Boundedness Detection. In: Falsafi, B., VijayKumar, T.N. (eds) Power-Aware Computer Systems. PACS 2004. Lecture Notes in Computer Science, vol 3471. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11574859_10
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DOI: https://doi.org/10.1007/11574859_10
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