Abstract
Coarse-grain reconfigurable architectures have been a matter of intense research in the last few years. They promise to be more adequate for computational tasks due to their better efficiency and bigger speed. As the coarse granularity implies also a reduction of flexibility, a universal architecture seems to be hardly feasible. Based on the KressArray architecture family, a design-space exploration system is being implemented, which supports the designer in finding an appropriate architecture for a given application domain. By analysing the results of a number of different experimental mappings, the system derives suggestions how the architecture can be enhanced. This paper presents an analyser tool, which allows the generation of such suggestions using approximate reasoning based on fuzzy logic. The tool is flexible enough to support different data gathering methods and an extensible rule set.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
E. Mirsky, A. DeHon: “MATRIX: A Reconfigurable Computing Architecture with Configurable Instruction Distribution and Deployable Resources”, Proc. FPGAs for Custom Computing Machines, pp. 157–166, IEEE CS Press, Los Alamitos, CA, U.S.A., 1996.
A. Marshall et al.: A Reconfigurable Arithmetic Array for Multimedia Applications; FPGA’99, Int’l Symposium on Field Programmable Gate Arrays, Monterey, CA, U.S.A., Febr. 21–23, 1999
C. Ebeling, D. Cronquist, P. Franklin: “RaPiD: Reconfigurable Pipelined Datapath”, Int’l Workshop on Field Programmable Logic and Applications, FPL’96, Darmstadt, Germany, Sept 1996.
R. A. Bittner, P. M. Athanas and M. D. Musgrove: “Colt: An Experiment in Wormhole Run-time Reconfiguration”; SPIE Photonics East’ 96, Boston, MA, USA, November 1996.
R. Kress: “A Fast Reconfigurable ALUs for Xputers”, Ph.D. thesis, Univ. Kaiserslautern, 1996.
E. Waingold et al.: “Baring it all to Software: Raw Machines”, IEEE Computer 30, pp. 86–93.
S. C. Goldstein, H. Schmit, et al.: “PipeRench: A Coprocessor for Streaming Multimedia Acceleration”; Int’l Symposium on Computer Architecture 1999, Atlanta, GA, USA, May 1999.
J. Rabaey. “Low-Power Silicon Architectures for Wireless Communications”; Embedded Tutorial, ASP-DAC 2000, Yokohama, Japan, Jan. 2000
R Hartenstein: “Mikroprozessor im Neuen Jahrtausend”; Elektronik, Januar 1000
R. Hartenstein (invited paper): The Microprocessor is no more General Purpose: why Future Reconfigurable Platforms will win; Int’l Conf. on Innovative Systems in Silicon, ISIS’97, Austin, Texas, USA, Oct 1997
R. Hartenstein, M. Herz, Th. Hoffmann, U. Nageldinger: “Mapping Applications onto Reconfigurable KressArrays”; International Workshop on Field Programmable Logic and Applications, FPL’99, Glasgow, Scotland, August/September 1999.
R. Hartenstein, M. Herz, Th. Hoffmann, U. Nageldinger: “Synthesis and Domain-specific Optimization of KressArray-based Reconfigurable Computing Engines”, Asia and South Pacific Design Automation Conference, ASP-DAC 2000, Yokohama, Japan, January 2000.
R. Kress et al.: “A Datapath Synthesis System for the Reconfigurable Datapath Architecture”; Asia and South Pacific Design Automation Conference, ASP-DAC’95, Makuhari, Chiba, Japan, August 29–September 1, 1995.
R. Hartenstein: “Reconfigurable Computing”; HighSys’ 99, Sindelfingen, Germany, Oct. 1999
C. A. Moritz, D. Yeung, A. Agarwal: “Exploring Optimal Cost-Performance Designs for Raw Microprocessors”; Int’l symposium on FPGAs for Custom Computing Machines, FCCM’98, Napa, CA, April 1998.
L. Guerra, M. Potkonjak and J. Rabaey: “A Methodology for Guided Behavioral-Level Optimization”; Proceedings of the 35th Design Automation Conference 1998 (DAC’98), June 15–19, 1998, San Francisco, CA, USA.
L. Guerra, M. Potkonjak and J. Rabaey: “System-Level Design Guidance Using Algorithm Properties”; IEEE VLSI Signal Processing Workshop, 1994.
W. Pedrycz: “Fuzzy Modelling — Paradigms and Practice”; Kluwer Academic Publishers, 1996.
B.R. Gaines: “Foundations of Fuzzy Reasoning”; Int’l Journal of Man-Machine Studies, Vol. 8, 1976.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2000 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Hartenstein, R., Herz, M., Hoffmann, T., Nageldinger, U. (2000). Generation of Design Suggestions for Coarse-Grain Reconfigurable Architectures. In: Hartenstein, R.W., Grünbacher, H. (eds) Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing. FPL 2000. Lecture Notes in Computer Science, vol 1896. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44614-1_42
Download citation
DOI: https://doi.org/10.1007/3-540-44614-1_42
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-67899-1
Online ISBN: 978-3-540-44614-9
eBook Packages: Springer Book Archive