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Performance Penalty for Fault Tolerance in Roving STARs

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Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing (FPL 2000)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1896))

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Abstract

In this paper we analyze the performance penalty of a fault-tolerant (FT) adaptive computing system (ACS) that implements the roving Self Testing AReas (STARs) approach for on-line testing and fault tolerance for FPGAs[1,5]. For most benchmarks, the presence of the STARs increases the critical path delay by 4.6% to 22%, and preallocating spare cells for fault tolerance causes an additional increase of up to 37%. We also present a procedure for estimating the worst case performance penalty caused by an incremental change of an already placed and routed FPGA. This estimate can be used to guide the selection of fault-tolerant reconfigurations to minimize their impact on the system timing. Our results show that the estimate is within 10% of the real delay values.

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Author information

Authors and Affiliations

  1. Dept of Electrical and Computer Engineering, University of North Carolina at Charlotte, USA

    John M. Emmert & Charles E. Stroud

  2. Dept of Electrical Engineering, University of Kentucky, USA

    Jason Cheatham, Andrew M. Taylor & Pankaj Kataria

  3. Bell Labs - Lucent Technologies, Murray Hill, NJ

    Miron Abramovici

Authors
  1. John M. Emmert
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  2. Charles E. Stroud
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  3. Jason Cheatham
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  4. Andrew M. Taylor
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  5. Pankaj Kataria
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  6. Miron Abramovici
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Editor information

Editors and Affiliations

  1. Computer Science Department, University of Kaiserslautern, P. O. Box. 30 49, 67653, Kaiserslautern, Germany

    Reiner W. Hartenstein

  2. Carinthia Tech Institute, Richard-Wagner-Str. 19, 9500, Villach, Austria

    Herbert Grünbacher

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© 2000 Springer-Verlag Berlin Heidelberg

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Emmert, J.M., Stroud, C.E., Cheatham, J., Taylor, A.M., Kataria, P., Abramovici, M. (2000). Performance Penalty for Fault Tolerance in Roving STARs. In: Hartenstein, R.W., Grünbacher, H. (eds) Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing. FPL 2000. Lecture Notes in Computer Science, vol 1896. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44614-1_59

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  • DOI: https://doi.org/10.1007/3-540-44614-1_59

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-67899-1

  • Online ISBN: 978-3-540-44614-9

  • eBook Packages: Springer Book Archive

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