Abstract
Currently, several design barriers inhibit the implementation of high-precision digital signal processing (DSP) systems with field programmable logic (FPL) devices. A new demonstration of the synergy between the residue number system (RNS) and FPL technology is presented in this paper. The quantifiable benefits of this approach are studied in the context of a high-end communications digital receiver. A new RNS-based direct digital synthesizer (DDS) that does not need a scaler circuit is introduced. The programmable decimation FIR filter is based on the arithmetic benefits associated with Galois fields and supports tuning the IF frequency as well as its bandwidth. Results show the proposed methodology requires fewer resources than classical designs, while throughput advantage is about 65%.
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Ramírez, J., García, A., Meyer-Baese, U., Lloris, A. (2002). Fast RNS FPL-based Communications Receiver Design and Implementation. In: Glesner, M., Zipf, P., Renovell, M. (eds) Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream. FPL 2002. Lecture Notes in Computer Science, vol 2438. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-46117-5_50
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DOI: https://doi.org/10.1007/3-540-46117-5_50
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