A Flexible Model of a CMOS Field Programmable Transistor Array Targeted for Hardware Evolution

Abstract

This article focuses on the properties of a fine grained reconfigurable transistor array currently under test at the Jet Propulsion Laboratory (JPL). This Field Programmable Transistor Array (FPTA) is integrated on a Complementary Metal-Oxide Semiconductor (CMOS) chip. The FPTA has advantageous features for hardware evolutionary experiments when compared to programmable circuits with a coarse level of granularity. Although this programmable chip is configured at a transistor level, its architecture is flexible enough to implement standard analog and digital circuits’ building blocks with a higher level of complexity. This model and a first set of evolutionary experiments have been recently introduced. Here, the objective is to further illustrate its flexibility and versatility for the implementation of a variety of circuits in comparison with other models of re-configurable circuits. New evolutionary experiments are also presented, serving as a basis for the authors to devise an improved model for the FPTA, to be fabricated in the near future.