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A Blocking Algorithm for FFT on Cache-Based Processors

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High-Performance Computing and Networking (HPCN-Europe 2001)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 2110))

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Abstract

In this paper, we propose a blocking algorithm for computing large one-dimensional fast Fourier transform (FFT) on cache-based processors. Our proposed FFT algorithm is based on the six-step FFT algorithm. We show that the block six-step FFT algorithm improves performance by effectively utilizing the cache memory. Performance results of one-dimensional FFTs on the Sun Ultra 10 and PentiumIII PC are reported. We succeeded in obtaining performance of about 108MFLOPS on the Sun Ultra 10 (UltraSPARC-IIi 333MHz) and about 247MFLOPS on the 1GHz PentiumIII PC for 220-point FFT.

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References

  1. D.H. Bailey, “FFTs in external or hierarchical memory,” The Journal of Supercomputing, vol. 4, pp. 23–35, 1990.

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  4. K.R. Wadleigh, “High performance FFT algorithms for cache-coherent multiprocessors,” The International Journal of High Performance Computing Applications, vol. 13, pp. 163–171, 1999.

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© 2001 Springer-Verlag Berlin Heidelberg

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Takahashi, D. (2001). A Blocking Algorithm for FFT on Cache-Based Processors. In: Hertzberger, B., Hoekstra, A., Williams, R. (eds) High-Performance Computing and Networking. HPCN-Europe 2001. Lecture Notes in Computer Science, vol 2110. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-48228-8_58

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  • DOI: https://doi.org/10.1007/3-540-48228-8_58

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-42293-8

  • Online ISBN: 978-3-540-48228-4

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