Abstract
Sorting is an important operation for a number of embedded applications. As sorting large datasets may impose undesired performance degradation, acceleration units coupled to the embedded processor can be an interesting solution for speeding-up the computations. This paper presents and evaluates three hardware sorting units, bearing in mind embedded computing systems implemented with FPGAs. The proposed architectures take advantage of specific FPGA hardware resources to increase efficiency. Experimental results show the differences in resources and performances among the three proposed sorting units and also between the sorting units and pure software implementations for sorting.We show that a hybrid between an insertion sorting unit and a merge FIFO sorting unit provides a speed-up between 1.6 and 25 compared to a quicksort software implementation.
Chapter PDF
Similar content being viewed by others
References
Golab L., Özsu M.T.: Issues in data stream management, ACM SIGMOD Record, v.32 n.2, p.5–14, June, San Diego, California (2003)
Govindaraju, N., Raghuvanshi, N., Henson, M., Tuft, D., Manocha, D.: GPUTera- Sort: high performance graphics co-processor sorting for large database management, in Proceedings of the 2006 ACM SIGMOD international conference on Management of data, June 26-29, Chicago, IL, USA (2006)
Knuth, D.E.:The Art of Computer Programming, Vol. 3 - Sorting and Searching. Addison- Wesley (1973)
Rajiv, R.D.P.:Accelerating Quicksort on the Intel® Pentium® 4 Processor with Hyper- Threading Technology, http://softwarecommunity.intel.com/articles/eng/2422.htm, October (2007)
Batcher, K.:Sorting Networks and Their Applications. Proc. AFIPS Spring Joint Computer Conf. Vol. 32, pp. 307–314, Atlantic City, NJ, USA, 30 April - 2 May (1968)
Martínez J., Cumplido, R.R., Feregrino, C.:An FPGA-based parallel sorting architecture for the Burrows Wheeler transform, Proceedings International Conference on Reconfigurable Computing and FPGAs, 28-30 Sept., Puebla City, Mexico (2005)
Zhang, Y., Zheng, S.Q.: An Efficient Parallel VLSI Sorting Architecture, VLSI Design, vol. 11, no. 2, pp. 137–147, (2000)
Lin, C.S., Liu, B.D. :Design of a Pipelined and Expandable sorting Architecture with Simple Control Scheme. IEEE International Symposium on Circuits and Systems, Volume: 4, pp. 217–220, 26-29 May. Scottsdale, Arizona, USA (2002)
Parhami, B., Kwai, D.M.: Data-driven control scheme for linear arrays. Application to a stable insertion sorter, IEEE Trans. On Parallel and Distributed Systems, January 1999, Vol. 10, No. 1, pp. 23–28, (1999)
Bednara, M., Beyer, O., Teich, J., Wanka, R.: Tradeoff Analysis And Architecture Design Of Hybrid Hardware/Software Sorter, Application-Specific Systems, Architectures, and Processors. Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors, Proceedings, pp. 299, 10-12 July, Boston, MA, USA (2000)
Ratnayake, K., Amer, A.: An FPGA Architecture of Stable-Sorting on a Large Data Volume : Application to Video Signals, 41st Annual Conference on Information Sciences and Systems, pp. 431–436, 14-16 March, Baltimore, USA (2007)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2008 Springer Science+Business Media, LLC
About this paper
Cite this paper
Marcelino, R., Neto, H., Cardoso, J.M. (2008). Sorting Units for FPGA-Based Embedded Systems. In: Kleinjohann, B., Wolf, W., Kleinjohann, L. (eds) Distributed Embedded Systems: Design, Middleware and Resources. DIPES 2008. IFIP – The International Federation for Information Processing, vol 271. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-09661-2_2
Download citation
DOI: https://doi.org/10.1007/978-0-387-09661-2_2
Publisher Name: Springer, Boston, MA
Print ISBN: 978-0-387-09660-5
Online ISBN: 978-0-387-09661-2
eBook Packages: Computer ScienceComputer Science (R0)