In this paper, various concepts of multi-gate transistors are discussed with regards to their technological feasibility and manufacturability. In addition, non-standard fabrication process modules for triplegate nanoscale MOSFETs and sub-10 nm nanowires are presented. Alternatives to costly extreme ultraviolet (EUV) lithography are proposed as well as a self-aligned nickel silicide module to reduce inherent parasitic access resistances.
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Lemme, M.C., Gottlob, H.D.B., Kurz, H. (2007). Non-Planar Devices for Nanoscale CMOS. In: Hall, S., Nazarov, A.N., Lysenko, V.S. (eds) Nanoscaled Semiconductor-on-Insulator Structures and Devices. NATO Science for Peace and Security Series B: Physics and Biophysics. Springer, Dordrecht. https://doi.org/10.1007/978-1-4020-6380-0_2
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DOI: https://doi.org/10.1007/978-1-4020-6380-0_2
Publisher Name: Springer, Dordrecht
Print ISBN: 978-1-4020-6378-7
Online ISBN: 978-1-4020-6380-0
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