Abstract
This chapter describes the architecture, design, analysis, and simulation and measurement results of the 3D-MAPS (3D massively parallel processor with stacked memory) chip built with a 1.5 V, 130 nm process technology, and a two-tier 3D stacking technology using 1.2 um-diameter, 6 um-height through-silicon vias (TSVs) and 3.4 um-diameter face-to-face bonding pads. 3D-MAPS consists of a core tier containing 64 cores and a memory tier containing 256 KB SRAM. Each core communicates with its dedicated 4 KB SRAM using face-to-face bonding pads. The maximum feasible memory bandwidth of 3D-MAPS is extremely wide (70.9 GB/s at 277 MHz) while the data transfer delay between the core tier and the memory tier is negligible. The maximum operating frequency is 277 MHz, the peak measured memory bandwidth usage is 63.8 GB/s, and the peak measured power is approximately 4 W based on eight parallel benchmarks.
The materials presented in this chapter are based on [7].
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Notes
- 1.
The footprint area given to us as part of 2009 DARPA/Tezzaron 3D IC multi-project wafer run was 5 ×5 mm, and the size of core was determined so that we can fit the maximum number of cores.
- 2.
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Lim, S.K. (2013). 3D-MAPS: 3D Massively Parallel Processor with Stacked Memory. In: Design for High Performance, Low Power, and Reliable 3D Integrated Circuits. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-9542-1_20
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