Abstract
This chapter discusses design techniques for dealing with design flexibility, in addition to complexity that was discussed in the previous chapter. Design techniques for managing adjustable number or antennas, modulations, number of sub-carriers and search algorithms will be presented. Multi-core architecture, based on scalable processing element will be described. At the end, flexibility for multi-band operation will be discussed, with emphasis on flexible FFT that operates over many signal bands. Area and energy cost of the added flexibility will be analyzed.
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References
Yang C-H, Marković D (2008) "A Multi-Core Sphere Decoder VLSI Architecture for MIMO Communications," in Proc. IEEE Global Communications Conf, Dec, pp 3297–3301
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Yang C-H, Yu T-H, Marković D (Mar. 2012) "Power and Area Minimization of Reconfigurable FFT Processors: A 3GPP-LTE Example," IEEE J. Solid-State Circuits 47(3):757–768
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Marković, D., Brodersen, R.W., Yang, CH. (2012). MHz-rate Multi-Antenna Decoders: Flexible Sphere Decoder Chip Examples. In: DSP Architecture Design Essentials. Electrical Engineering Essentials. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-9660-2_15
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DOI: https://doi.org/10.1007/978-1-4419-9660-2_15
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