Abstract
This paper considers performance prediction for various computer networks in terms of the number of references made to the memory. Analytical solutions were obtained for the models with multiple requests to the memory and parallel access to one memory bank with a Negative Exponential distribution of requests generated by CPUs. Numerical simulation was carried out for Hyper-cube, Cube Connected Cycle and Torus processor networks. The distributed parallel architectures investigated could be viewed as PRAM simulating models. The analytical solutions are compared to numerical simulation results.
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© 1992 Springer-Verlag London
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Chochia, G. (1992). On the Performance Prediction of PRAM Simulating Models. In: Hillston, J.E., King, P.J.B., Pooley, R.J. (eds) 7th UK Computer and Telecommunications Performance Engineering Workshop. Workshops in Computing. Springer, London. https://doi.org/10.1007/978-1-4471-3538-8_4
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DOI: https://doi.org/10.1007/978-1-4471-3538-8_4
Publisher Name: Springer, London
Print ISBN: 978-3-540-19733-1
Online ISBN: 978-1-4471-3538-8
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