Switch Line Fault Diagnosis in FPGA Interconnects Using Line Tracing Approach

Abstract

This paper aims at fault detection and location in interconnect of a Field Programmable gate array. We discuss the testing of interconnect types like single lines, double lines, global interconnect, Long length lines, switching matrices, Buffer drivers, Quad lines and direct lines. The proposed testing scheme uses a test manager which defines a part of the chip as the pattern generator and the other half as response analyzer. The chip is reconfigured several times to cover all portions of interconnect. The outcome of each reconfiguration is a bit which provides a pass or fail result. Testing is done in two phases, phase one involves several reconfigurations intended to detect various faults in the interconnect structure. The test manager provides the required test sequence in each configuration. This phase involves extensively testing the complete interconnect structure for all possible faults namely, configurable interconnection points struck on, configurable interconnection points struck off, wire struck-at-1, wire struck-at-0, two adjacent wires short and wires open.