Skip to main content

A Sampled-Data CMOS VLSI Implementation of a Multi-Character ANN Recognition System

  • Chapter
VLSI Artificial Neural Networks Engineering
  • 194 Accesses

Abstract

Artificial Neural Networks (ANNs) are successfully applied to a variety of data classification and recognition problems. Through experimentation and simulation, acceptable solutions to such problems can be obtained using ANNs. However, the effectiveness of an ANN algorithm strongly depends on the hardware that executes it. This hardware has to capture the inherent parallelism of the ANNs and tolerate the ANN’s need of massive numbers of computations.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 129.00
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 169.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 169.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

Similar content being viewed by others

References

  1. Bernstein, J., “Profiles: Marvin Minsky,” The New Yorker, pp.50-126, December 1981.

    Google Scholar 

  2. Hay, J., Martin, E, and Wightman, C., “The MARK I Perceptron, Design and Performance,” IRE International Convention Record: Part 2, New York: IRE, pp.78-87, 1960.

    Google Scholar 

  3. Widrow, B., and Hoff, M., “Adaptive Switching Circuits,” WESCON Convention Record: Part 4, pp.96-104, 1960.

    Google Scholar 

  4. Crane, H., “Neuristor: A Novel Device and System Concept,” Proceedings of the IRE, 50, pp.2048-2060, 1962.

    Article  Google Scholar 

  5. Hecht-Nielsen, R., “Performance of Optical, Electro-Optical, and Electronic Neurocomputers,” Proceedings of the SPIE, 634, pp.277-306, 1986.

    Article  Google Scholar 

  6. Farhat, N., Psaltis, D., Prata, A., and Paek, E., “Optical Implementation of the Hopfield Model,” Applied Optics, 24, pp.1469-1475, 1985.

    Article  Google Scholar 

  7. Denker, J. (Ed.), “AIP Conference Proceedings 151: Neural Networks for Computing,” New York: American Institute of Physics, 1986.

    Google Scholar 

  8. Graf, H. P., Jackel, L., and Hubbard, W., “VLSI Implementation of a Neural Network Model,” IEEE Computer, Volume 21, Number 3, pp.41-49, March 1988.

    Article  Google Scholar 

  9. Graf, H. P., et al., “A CMOS Associative Memory Chip,” Proceedings of IJCNN, Volume III, pp.461-468, 1987.

    Google Scholar 

  10. Jackel, L., et al., “Artificial Neural Networks for Computing,” Journal of Vacuum Science & Technology B (Microelectronics: Processing and Phenomena), Volume 4, Number 1, pp.61-63, January/February 1986.

    Article  Google Scholar 

  11. Mead, C., and Mahowald, M., “A Silicon Model of Early Visual Processing,” Neural Networks, 1, pp.91-97, 1988.

    Article  Google Scholar 

  12. Paulos, J. J., and Hollis, P. W., “Neural Networks using Analog Multipliers,” Proceedings of IEEE ISCAS, Volume I, pp.499-502, 1988.

    Google Scholar 

  13. Verleysen, M., et al., “Neural Networks for High-Storage Content-Addressable Memory: VLSI Circuit and Learning Algorithm, ” IEEE Journal of Solid State Circuits, Volume 24, Number 3, pp.562-569, June 1989.

    Article  Google Scholar 

  14. Rossetto, O., et al., “Analog VLSI Synaptic Matrices as Building Blocks for Neural Networks,” IEEE Micro, Volume 9, Number 6, pp.56-63, December 1989.

    Article  Google Scholar 

  15. Jou, I. C., Wu, C., and Liu, R., “Programmable SC Neural Networks for Solving Nonlinear Programming Problems,” Proceedings of IEEE IS-CAS, Volume II, pp.2837-2840, 1990.

    Google Scholar 

  16. Holler, M., et al., “An Electrically Trainable Artificial Neural Network (ETANN) with 10240 Floating Gate Synapses,” Proceedings of IEEE IJCNN, Washington DC, Volume II, pp.191-196, June 1989.

    Google Scholar 

  17. Abu-Mostafa, Y. S., and Pslatis, D., “Optical Neural Computers,” Scientific American, 256, pp.88-95, March 1987.

    Article  Google Scholar 

  18. Farhat, N., Miyahara, S., and Lee, K. S., “Optical Analog of Two-Dimensional Neural Networks and Their Application in Recognition of Radar Targets,” In J. Denker (Ed.), “AIP Conference Proceedings 151: Neural Networks for Computing,” New York: American Institute of Physics, pp.146-152, 1986.

    Google Scholar 

  19. Hecht-Nielsen, R., “Neural-Computing: Picking the Human Brain,” IEEE Spectrum, Volume 25, Number 3, pp.36-41, March 1988.

    Article  Google Scholar 

  20. Simpson, P., “Artificial Neural Systems: Foundations, Paradigms, Applications, and Implementations, ” McGraw-Hill/Pergamon Press, 1990.

    Google Scholar 

  21. Kung, S. Y., and J.N. Hwang, J. N., “Parallel Architectures for Artificial Neural Networks,” Proceedings of IEEE IJCNN, San Diego, Volume II, pp.165-172, June 1988.

    Google Scholar 

  22. Akers, L. A., and Walker, M. R., “A Limited Interconnect Synthetic Neural IC,” Proceedings of IEEE IJCNN, San Diego, Volume II, pp.151-157, June 1988.

    Google Scholar 

  23. Suzuki, Y., and Atlas, L. E., “A Study of Regular Architectures for Digital Implementation of Neural Networks,” Proceedings of IEEE International Symposium on Circuits and Systems, pp.82-85, May 1989.

    Google Scholar 

  24. Tamberg, J., et al., “Fully Digital Neural Network Implementation Based on Pulse Density Modulation,” Proceedings of IEEE Custom Integrated Circuits Conference, Paper 12.7, May 1989.

    Google Scholar 

  25. Weinfield, M., “A Fully Digital Integrated CMOS Hopfield Network Including the Learning Algorithm,” In J. G. Delgado-Farias and W. R. Moore (Editors), “VLSI for Artificial Intelligence,” Kluwer Academic Publishers, Boston, 1989.

    Google Scholar 

  26. Yasunaga, M., et al., “A Wafer Scale Integration Neural Network Utilizing Completely Digital Circuits,” Proceedings of IEEE IJCNN, Washington DC, Volume II, pp.213-217, June 1989.

    Google Scholar 

  27. Raffel, J., et al., “A Generic Architecture for Wafer-Scale Neuromorphic Systems,” Proceedings of IEEE First ICNN, San Diego, Volume III, pp.501-513, June 1987.

    Google Scholar 

  28. Graf, H.P., and Jackel, L., “Analog Electronic Neural Network Circuits,” IEEE Circuits and Devices Magazine, Volume 5, Number 4, pp.44-49&55, July 1989.

    Article  Google Scholar 

  29. Tsividis, Y., and Anastassiou, D., “Switched-Capacitor Neural Networks,” Electronics Letters, Volume 23, Number 18, pp.958-959, August 1987.

    Article  Google Scholar 

  30. Rodriguez-Vazquez, A., et al., “Switched-Capacitor Neural Networks for Linear Programming,” Electronics Letters, Volume 24, Number 8, pp.496-498, April 1988.

    Article  Google Scholar 

  31. Horio, Y., et al., “Speech Recognition Network with SC Neuron-Like Components,” IEEE ISCAS, Volume I, pp.495-498, 1988.

    Google Scholar 

  32. Redman-White, W., et al., “A Limited Connectivity Switched Capacitor Analogue Neural Processing Circuit with Digital Storage of Non-Binary Input Weights,” IEE ICANN, London, Number 313, pp.42-46, 1989.

    Google Scholar 

  33. Hansen, J.E., Skelton, J.K., and Allstot, D.J., “A Time-Multiplexed Switched-Capacitor Circuit for Neural Network Applications, ” IEEE International Symposium on Circuits and Systems, Volume II, pp.2177-2180, 1989.

    Article  Google Scholar 

  34. Vallancourt, D., and Tsividis, Y., “Timing-Controlled Switched Analog Filters with Full Digital Programmability,” IEEE International Symposium on Circuits and Systems, Volume II, pp.329-333, 1987.

    Google Scholar 

  35. Murray, A.F., and Smith, A.V.W., “Asynchronous VLSI Neural Networks Using Pulse-Stream Arithmetic,” IEEE Journal of Solid-State Circuits, Volume SC-23, Number 3, pp.688-697, June 1988.

    Google Scholar 

  36. Murray, A.F., et al., “Pulse-Stream VLSI Networks Mixing Analog and Digital Techniques,” IEEE Transactions on Neural Networks, Volume 2, Number 2, pp.193-204, March 1991.

    Article  Google Scholar 

  37. Kaehler, J.A., “Periodic-Switched Filter Networks: A Means of Amplifying and Varying Transfer Functions,” IEEE Journal of Solid-State Circuits, Volume SC-4, pp.225-230, August 1969.

    Article  Google Scholar 

  38. Bruton, L.T., and Pederson, R.T., “Tunable RC-Active Filters Using Periodically Switched Conductances,” IEEE Transactions on Circuit Theory, Volume CT-20, pp.294-301, May 1973.

    Google Scholar 

  39. Liou, M.L., “Exact Analysis of Linear Circuits Containing Periodically Operated Switches with Applications,” IEEE Transactions on Circuit Theory, Volume CT-19, pp.146-154, March 1972.

    Article  Google Scholar 

  40. Rehan, S.E., “Design Considerations for Switched-Resistor Active Filters,” M.Sc. Thesis, Al-Mansoura University, Egypt, December 1987.

    Google Scholar 

  41. Vallancourt, D., and Tsividis, Y., “A Fully Programmable Sampled-Data Analog CMOS Filter with Transfer-Function Coefficients Determined by Timing,” IEEE Journal of Solid-State Circuits, Volume SC-22, Number 6, pp.1022-1030, December 1987.

    Article  Google Scholar 

  42. Alspector, J., and Allen, R.B., “A Neuromorphic VLSI Learning System,” in Proceedings of the 1987 Stanford Conference, Losleben, P., (Editor), “Advanced Research in VLSI,” MIT Press, Cambridge, MA, pp.313-349, 1987.

    Google Scholar 

  43. Tsividis, Y., and Satyanarayana, S., “Analogue Circuits for Variable-Synapse Electronic Neural Networks,” Electronics Letters, Volume 23, Number 24, pp.1313-1314, November 1987.

    Article  Google Scholar 

  44. Gregorian, R., and Temes, G.C., “Analog MOS Integrated Circuits for Signal Processing,” John-Wiley & Sons, NY, 1986.

    Google Scholar 

  45. Uyemura, J.P., “Fundamentals of MOS Digital Integrated Circuits,” Addison-Wesley Publishing Company, 1988.

    Google Scholar 

  46. Rehan, S.E., and Elmasry, M.I., “A Novel CMOS Sampled-Data VLSI Implementation ofANNs, ” Electronics Letters, Volume 28, No. 13, pp.1216-1218, June 1992.

    Article  Google Scholar 

  47. Rumelhart, D., and McClelland, J., “Parallel Distributed Processing: Explorations in the Microstructure of Cognition: Volumes 1 and 2,” Cambridge: Bradford Books/MIT Press, 1986.

    Google Scholar 

  48. Rehan, S.E., and Elmasry, M.I., “VLSI Implementation of a Prototype MLP Using Novel Programmable Switched-Resistor CMOS ANN Chip,” The 1993 World Congress on Neural Networks (WCNN’93), Portland, Oregon, pp. 96-99, July, 1993.

    Google Scholar 

  49. Rehan, S.E., and Elmasry, M.I., “Modular Switched-Resistor ANN Chip for Character Recognition Using Novel Parallel VLSI Architecture,” Neural, Parallel & Scientific Computations journal, 1, pp.241-262, 1993.

    MATH  Google Scholar 

  50. Rehan, S.E., and Elmasry, M.I., “VLSI Implementation of Modular ANN Chip for Character Recognition,” 36th Midwest Symposium on Circuits and Systems, Windsor, August 16-18, 1993.

    Google Scholar 

  51. Rehan, S.E., and Elmasry, M.I., “VLSI Zip-Code Recognition System Using Artificial Neural Network,” The Fifth International Conference on Microelectronics (ICM’93), Dhahran, Saudi Arabia, pp.294–297, December 14-16, 1993.

    Google Scholar 

Download references

Authors

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 1994 Springer Science+Business Media New York

About this chapter

Cite this chapter

Rehan, S.E., Elmasry, M.I. (1994). A Sampled-Data CMOS VLSI Implementation of a Multi-Character ANN Recognition System. In: Elmasry, M.I. (eds) VLSI Artificial Neural Networks Engineering. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-2766-4_2

Download citation

  • DOI: https://doi.org/10.1007/978-1-4615-2766-4_2

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4613-6194-7

  • Online ISBN: 978-1-4615-2766-4

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics