Abstract
The analysis of today’s neural paradigms brings to light a set of elementary compute-intensive algorithmic strings which are shared by all neural models and, thus, make sense to be implemented in hardware. 2-D arrays composed of a specific VLSI Neural Signal Processor MA 16 that integrates these elementary strings as hard-wired functional blocks present a favourable solution to the architectural problem of mapping neural parallelity and adaptivity into silicon. The proposed neurocomputer concept is sizeable independently to the applicational domain in terms of processing power, memory size and flexibility, and is designed for throughputs that enable the user to access real-world applications in reasonable time. At the chip site, throughput rates of the order of 500 MC/sec (1 Connection = 16 bit) are achievable with 1μm CMOS technology. 2-dimensional systolic arrays composed of 16x16 MA16 chips will allow for processing of 128 GC/sec.
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Ramacher, U. et al. (1991). Design of a 1st Generation Neurocomputer. In: Ramacher, U., Rückert, U. (eds) VLSI Design of Neural Networks. The Springer International Series in Engineering and Computer Science, vol 122. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-3994-0_14
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DOI: https://doi.org/10.1007/978-1-4615-3994-0_14
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