Abstract
SDEF, a systolic array programming system, is presented. It is intended to provide 1) systolic algorithm researchers/developers with an executable notation, and 2) the software systems community with a target notation for the development of higher level systolic software tools. The design issues associated with such a programming system are identified. A spacetime representation of systolic computations is described briefly in order to motivate SDEF’s program notation. The programming system treats a special class of systolic computations, called atomic systolic computations, any one of which can be specified as a set of properties: the computation’s 1) index set (S), 2) domain dependencies (D), 3) spacetime embedding (E), and nodal function (F). These properties are defined and illustrated. SDEF’s user interface is presented. It comprises an editor, a translator, a domain type database, and a systolic array simulator used to test SDEF programs. The system currently runs on a Sun 3/50 operating under Unix and Xwindows. Key design choices affecting this implementation are described. SDEF is designed for portability. The problem of porting it to a Transputer array is discussed.
This work was supported by the Office of Naval Research under contracts N00014-84-K-0664 and N00014-85-K-0553.
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References
Allen, K. R., And R. P. Pargas, “On Compiling Loop Algorithms onto Systolic Arrays,” TR #85–11–18, Clemson University, Dept. of Computer Science, 1985.
Annaratone, M., E. Arnould, R. Cohen, T. Gross, H-T Kung, M. Lam, O. Mensilcioglu, K. Sarocky, J. Senko, And J Webb, “Architecture of Warp,” Proc. COMPCON, Spring 1987.
Bruegge, B., C. Chang, R. Cohen, T. Gross, M. Lam, P. Lieu, A. Noaman, And D. Yam, “Programming Warp,” Proc. COMPCON, Spring 1987.
Cappello, P. R., VLSI Architectures for Digital Signal Processing, Princeton University, Ph.D. Dissertation, Princeton, NJ, Oct. 1982.
Cappello, P. R. And K. Steiglitz, “Unifying VLSI Array Design with Linear Transformations of Space-Time,” in Advances in Computing research, VLSI Theory, ed. F. P. Preparata, vol. 2, pp. 23–65, JAI Press, Inc., Greenwich, CT, 1984.
Chen, M. C., “Synthesizing Systolic Designs,” Proc. Sec. Int. Symp. VLSI Technology, Systems, and Applications, p. 209–215, Taipai, May 1985.
Chen, M. C., “A Parallel Language and Its Compilation to Muliprocessor Machines,” J. Parallel and Distributed Computing, Dec. 1986.
Delosme, J. M. And I. C. F. Ipsen, “Systolic Array Synthesis: Computability and Time Cones,” Yale/DCS/RR-474, May 1986.
Fisher, A. L., H-T Kung, L. M. Monier, Y. Dohi, “The Architecture of a Programmable Systolic Chip,” Journal VLSI and Computer Systems,1(2):153169, 1984.
Fortes, J. A. B. And D. I. Moldovan, “Parallelism detection and algorithm transformation techniques useful for VLSI architecture design;” J. Parallel Distrib. Comput., May 1985.
Fortes, J. A. B., K. S. Fu, And B. W. Wah, “Systematic Approaches to the Design of Algorithmically Spcified Systolic Arrays,” Proc. Int. Conf. on Acoustics, Speech, and Signal Processing, pp. 300–303, Tampa, 1985.
Foulser, D. E., And R. Schreiber, “The Saxpy Matrix-1: A General-Purpose Systolic Computer,” IEEE Computer, 20 (7): 35–43, June 1987.
Huang, C. H. And C. Lengauer, “An incremental mechanical development of systolic solutions to the algebraic path problem,” TR-86–28, Univ. of Texas, Dept. Computer Science, Austin, Dec. 1986.
Kapauan, A., K. Y. Wang, D. Gannon, J. Cuny, And L. Snyder, “The Pringle: and experimental system for parallel algorithm and software testing,” Proc Int. Conf. on Parallel Processing, 1984.
Karp, R. M., R.E. Miller, And S. Winograd, “Properties of a Model for Parallel Computations: Determinace, Termination, Queueing,” SIAM J. Appl. Math., 14: 1390–1411, 1966.
Karp, R. M., R.E. Miller, And S. Winograd, “The Organization of Computations for Uniform Recurrence Equations, ” J. of the Assoc. for Comput. Machinery, 14: 563–590, 1967.
Kernighan, B. And M. Ritchie, The C Programming Language, Prentice-Hall, Inc. Englewood Cliffs, NJ, 1978.
Kung, H-T And C. E. Leiserson, “Algorithms for VLSI Processor Arrays,” in Introduction to VLSI Systems, Addison-Wesley Publishing Co., Menlo Park, CA, 1980.
Kung, H-T, A Listing of Systolic Papers, Dept. of Computer Science, CanegieMellon Univ., Pittsburgh, Dec. 1986.
Kung, S-Y, K. S. Arun, R. J. Gal-Ezer, And D. V. B. Rao, “Wavefront array processor: Language, Architecture and Applications”, IEEE Trans. on Computers, C-31(11), May 1973.
Kung, S-Y, “On Supercomputing with Systolic/Wavefront Array Processors,” Proc. IEEE, 1984.
Li, G. J. And B. W. Wah, “The Design of Optimal Systolic Algortihms,” IEEE Trans. on Computers, C-34(1): 66–77, 1985.
Mccanny, J. V. And J. G. Mcwhirter, “The derivation and utilization of bit level systolic array architectures, ” Int. Workshop on Systolic Arrays, pp. F1.1-F1. 12, Univ. of Oxford, July 1986.
Miranker, W. L. And A. Winkler, “Spacetime Representations of Computational Structures,” Computing, Vol. 32, 1984.
Moldovan, D. I., “On the Analysis and synthesis fo VLSI algorithms,” IEEE Trans. Comput., C-31: 1121–1126, Nov. 1982.
Moldovan, D. I., “On the Design of Algorithms for VLSI Systolic Arrays, ” Proc. IEEE, 71 (1): 113–120, Jan 1983.
Moldovan, D. I. And J. A. B. Fortes, “Partitioning and Mapping Algorithms into Fixed Systolic Arrays,” IEEE Trans. on Computers, C-35: 1–12, 1986.
Moldovan, D. I., “Advis: A software Package for the Design of Systolic Arrays,” IEEE Trans. Computer-Aided Design, CAD-6(1): 33–40, Jan. 1987.
Navarro, J. J., J. M. Llaberia, And M. Valero “Partitioning: An Essential Step in Mapping Algorithms Into Systolic Array Processors,” IEEE Computer, 20 (7): 77–89, June 1987.
Nelis, H. W., And E. F. Deprettere “Methods and Tools for the Design and Partitioning of VLSI Systolic/Wavefront Arrays,” TR, Dept. of Electrical Engineering, Delft University of Technology, 1987.
Quinton, P., “Automatic synthesis of systolic arrays from uniform recurrent equations,” Proc. 11th Ann. Symp. on Computer Architecture, pp. 208–214, 1984.
Rao, S. K., “Regular Iterative Algorithms and Their Implementation on Processor Arrays,” Ph.D. Dissertation, Stanford University, Stanford, October 1985.
Snyder, L., “Parallel programming and the poker programming environment,” Computer, 17 (7): 27–36, July 1984.
Snyder, L., “A Dialect of the Poker Programming Environment Specialized for Systolic Computation,” Proc. Mt. Workshop on Systolic Arrays, Univ. of Oxford, July 1986.
Snyder, L. And D. Socha, “Poker on the Cosmic Cube: The First Retargetable Parallel Programming Language and Environment,” Proc Mt. Conf. on Parallel Processing, pp. 628–635, St. Charles, IL, August 1986.
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© 1988 Plenum Press, New York
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Engstrom, B.R., Cappello, P.R. (1988). The SDEF Systolic Programming System. In: Tewksbury, S.K., Dickinson, B.W., Schwartz, S.C. (eds) Concurrent Computations. Springer, Boston, MA. https://doi.org/10.1007/978-1-4684-5511-3_15
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