Abstract
Clock distribution and synchronization in synchronous systems are important issues especially as the size of the system and/or the clock rate increase. Minimization of clock skew has always been a major concern for the designers. Many factors contribute to clock synchronization and skew in a synchronous system. Among the major factors are: the clock distribution network, choice of clocking scheme, the underlying technology, the size of the system and level of integration, the type of material used in distributing the clock, clock buffers, and the clock rate. To be able to get around the problems related to clock skew and synchronization, one has to understand the effect that clock skew can have on the operation of a given system. In this paper we derive simple and practical formulations of these effects in terms of a few time-parameters that can be considered as properties of the individual modules and the clock network in a synchronous system. Knowing these time-parameters, one can determine the maximum throughput of a given system as well as its reaction to a change in clock skew. Three different clocking schemes, namely, edge-triggered, single-phase level sensitive, and two-phase clocking are considered. However, using the approaches discussed in this paper, the effect of clock skew for any other clocking scheme can be analyzed and formulated.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
J. W. Goodman, F. I. Leonberger, S-Y. Kung, and R. A. Athale, Optical interconnections for VLSI systems, Proc. IEEE, vol. 72, no. 7, July 1984, pp. 850–866.
S.Y. Kung and R.J. Gal-Ezer, Synchronous Versus Asynchronous Computation in Very Large Scale Integrated Array Processors, Proceedings of SPIE Symposium, Vol. 341 Real Time Signal Processing V, 1982, pp. 53–65.
Allan L. Fisher and H.T. Kung, Synchronizing Large VLSI Processor Arrays, IEEE Transactions on Computers, Vol. C-34, No. 8, Aug. 1985, pp. 734–740.
Donald F. Wann and Mark A. Franklin, Asynchronous and Clocked Control Structures for VLSI Based Interconnection Networks, IEEE Transactions on Computers, Vol. C-32, No. 3, March 1983, pp. 284–293.
H.B. Bakoglu, J.T. Walker and J.D. Meindl, A Symmetric Clock Distribution Tree and Optimized High-Speed Interconnections for Reduced Clock Skew in ULSI and WSI Circuits, IEEE International Conference on Computer Design, Rye Brook, NY, Oct. 1986, pp. 118–122.
E. G. Friedman and S. Powell, Design and Analysis of a Hierarchical Clock Distribution System for Synchronous Standard Cell/Macrocell VLSI, IEEE Journal of Solid-State Circuits, Vol. SC-21, No. 2, April 1986, pp. 240–246.
H.B. Bakoglu and J.D. Meindl, Optimal Interconnection Circuits for VLSI, IEEE Transactions on Electron Devices, Vol. ED-32, No. 5, May 1985, pp. 903–909.
M. Hatamian and G. L. Cash, A 70-MHz 8-bit x 8-bit parallel pipelined multiplier in 2.5 micron CMOS, J. Solid State Circuits, vol. SC-21, no. 4, Aug. 1986, pp. 505–513.
M. Hatamian and G. L. Cash, Parallel Bit-Level Pipelined VLSI designs for High Speed Signal Processing, Proc. IEEE, vol. 75, No. 9, pp. 1192–1202 (1987).
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 1988 Plenum Press, New York
About this chapter
Cite this chapter
Hatamian, M. (1988). Understanding Clock Skew in Synchronous Systems. In: Tewksbury, S.K., Dickinson, B.W., Schwartz, S.C. (eds) Concurrent Computations. Springer, Boston, MA. https://doi.org/10.1007/978-1-4684-5511-3_6
Download citation
DOI: https://doi.org/10.1007/978-1-4684-5511-3_6
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4684-5513-7
Online ISBN: 978-1-4684-5511-3
eBook Packages: Springer Book Archive