Abstract
This chapter describes and extends a recently developed approach for analyzing the performance of asynchronous circuits using stochastic timed Petri nets (STPNs) with unique- and free-choice and general delay distributions. The approach uses finite net executions to derive closed-form expressions for both upper and lower bounds of the performance metrics. The expressions can be efficiently evaluated using standard statistical methods. The mean of the upper and lower bounds provides an performance estimate which has a well-defined error interval. The error interval can often be made arbitrarily small by analyzing longer net executions at the cost of additional run-time. Experiments of several asynchronous circuits demonstrate the efficiency of the approach as well as the high quality of the estimates. The experiments include a fullscale STPN model of Intel’s asynchronous instruction length decoding and steering unit with over 900 transitions and 500 places.
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Xie, A., Beerel, P.A. (2000). Performance Analysis of Asynchronous Circuits and Systems Using Stochastic Timed Petri Nets. In: Yakovlev, A., Gomes, L., Lavagno, L. (eds) Hardware Design and Petri Nets. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-3143-9_13
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DOI: https://doi.org/10.1007/978-1-4757-3143-9_13
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