Skip to main content

A Comprehensive Survey on Strategies in Multicore Architectures, Design Considerations and Challenges

  • Conference paper
  • First Online:
Proceedings of International Conference on Artificial Intelligence, Smart Grid and Smart City Applications (AISGSC 2019 2019)

Abstract

CMOS technology in contemporary period is enhanced with advanced features and compatible storage system. Advanced CMOS technology provides functional density, increased performance, reduced power, etc. System-on-chip (SoC) technology provides a path for continual improvement in performance, power, cost, and size at the system level in contrast with the conventional CMOS scaling. When a single processor is transformed into multicore processor, it faces a lot of hazards to confine the circuits into single chip. To emphasize the importance of multicore architecture, this paper provides a comprehensive survey on multicore architectures designs, constraints, and practical issues.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 169.00
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 219.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 219.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Abbreviations

ALU:

Arithmetic logic unit

CMOS:

Complementary metal oxide semiconductor

CPU:

Central processing unit

DSP:

Digital signal processing

FPOA:

Field-programmable object array

FPU:

Floating point unit

I/O:

Input/output

IC:

Integrated circuit

IMAP:

Integrated memory array processor

KB:

Kilobyte

MAC:

Multiply-accumulate

NoC:

Network-on-chip

PE:

Processing element

RAM:

Random access memory

RISC:

Reduced instruction set computer

ROM:

Read-only memory

SoC:

System-on-chip

VLIW:

Very long instruction word

References

  1. Mohanty RP, Turuk AK, Sahoo B (2012) Analysing the performance of multi-core architecture. 1st International conference on Computing, Communication and Sensor Networks-CCSN, pp 1–6

    Google Scholar 

  2. Das B, Mahato AK, Khan AK (2013) Architecture and implementation issues of multicore processors and caching–a survey. Int J Res Eng Technol 2(2):78–82

    Google Scholar 

  3. Keung A, Rabaey JM (1995) A 2.4 GOPS data-driven reconfigurable multiprocessor IC for DSP. IEEE International conference on solid-state circuits, pp 108–110

    Google Scholar 

  4. Rixner S, Dally WJ, Kapasi UJ, Khailany B, Lopez Laguns A, Mattson P, Owens JD (1998) A bandwidth-efficient architecture for media processing. IEEE international symposium on microarchitecture (MICRO), pp 3–13

    Google Scholar 

  5. Khailany B, Dally WJ, Chang A, Kapasi UJ, Namkoong J, Towles B (2002) VLSI design and verification of the imagine processor. IEEE International conference on computer design, pp 289–294

    Google Scholar 

  6. Hammond L, Hubbert B, Siu M, Prabhu M, Chen M, Olukotun K (2000) The stanford hydra CMP. IEEE J Micro Archit 20(2):71–84

    Article  Google Scholar 

  7. Kyo S, Koga T, Okazaki S, Uchida R, Yoshimoto S, Kuroda I (2003) A 51.2 GOPS scalable video recognition processor for intelligent cruise control based on a linear array of 128 4-way VLIW processing elements. IEEE International conference on solid-state circuits, pp 48–49

    Google Scholar 

  8. Carlstrom J, Nordmark G, Roos J, Boden T, Svensson L, Westlund P (2004) A 40Gb/s network processor with RISC dataflow architecture. IEEE International conference on Solid-state circuits, pp 60–61

    Google Scholar 

  9. Swanson S, Michelson K, Schwerin A, Oskin M (2003) Wavescalar. IEEE international symposium On microarchitecture (MICRO), pp 291–302

    Google Scholar 

  10. Jones AM, Butts M (2006) TeraOPS hardware: a new massively-parallel MIMD computing fabric integrated circuit. In: Proceedings of IEEE hotchips symposium, pp 59–66

    Google Scholar 

  11. Pham D, Asano S, Bolliger M, Day MN, Hofstee HP, Johns C, Kahle J, Kameyama A, Keaty J, Masubuchi Y, Riley M, Shippy D, Stasiak D, Suzuoki M, Wang M, Warnock J, Weitzel S, Wendel D, Yamazaki T, Yazawa K (2005) The design and implementation of a first generation cell processor. IEEE international conference on solid-state circuits, pp 184–185

    Google Scholar 

  12. Intellasys Seaforth-24B Embedded array processor, technical report. http://www.intellasys.net/

  13. Waingold E, Taylor M, Srikrishna D, Sarkar V, Lee W, Lee V, Kim J, Frank M, Finch P, Barua R, Babb J, Amarasinghe S, Agarwal A (1997) Baring it all to software: raw machines. IEEE J Comp Soc 30(9):86–93

    Article  Google Scholar 

  14. Mai K, Paaske T, Jayasena N, Ho R, Dally WJ, Horowitz M (2000) Smart memories: a modular reconfigurable architecture. International symposium on computer architecture, pp 161–171

    Google Scholar 

  15. Oliver J, Rao R, Franklin D, Chong FT, Akella V (2005) Synchroscalar: evaluation of an embedded, multi-core architecture for media applications. J Embed Syst Spec Issue Multi-Core Archit:1–16

    Google Scholar 

  16. Zhang H, Prabhu V, George V, Wan M, Benes M, Abnous A, Rabaey JM (2000) A1-V heterogeneous reconfigurable DSP IC for wireless baseband digital signal processing. IEEE J Solid State Circuits (JSSC) 35(11):1697–1704

    Article  Google Scholar 

  17. Schmit H, Whelihan D, Moe M, Levine B, Taylor RR (2002) PipeRench: a virtualized programmable datapath in 0.18 micron technology. IEEE Custom Integrated Circuits Conference (CICC), pp 63–66

    Google Scholar 

  18. Baines R, Pulley D (2003) A Total cost approach to evaluating different reconfigurable architectures for baseband processing in wireless receivers. IEEE Commun Mag 41(1):105–113

    Article  Google Scholar 

  19. Cronquist DC, Franklin P, Fisher C, Figuerar M, Ebeling C (1999) Architecture design of re-configurable pipelined datapaths, Conference on Advanced Research in VLSI, pp 23–40

    Google Scholar 

  20. Xanthopoulos T, Chandrakasan AP (2000) A low-power DCT core using adaptive bit width and arithmetic activity exploiting signal correlations and Quantization. IEEE J Solid State Circuit 35(5):740–750

    Article  Google Scholar 

  21. Vangal S, Howard J, Ruhl G, Dighe S, Wilson H, Tschanz J, Finan D, Lyer P, Singh A, Jacb T, Jain S, Venkataraman S, Hoskote Y, Borkar N (2007) An 80-tile 1.28 TFLOPS network on-chip in 65nm CMOS. IEEE International conference on solid-state circuits, pp 98–99

    Google Scholar 

  22. Kasapaki E, Schoeberl M, Sørensen RB, Müller C, Goossens K, Sparso J (2015) Argo: a real-time network-on-chip architecture with an efficient GALS implementation. IEEE transactions on very large scale integration systems, pp 1–14

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2020 Springer Nature Switzerland AG

About this paper

Check for updates. Verify currency and authenticity via CrossMark

Cite this paper

Radhika, R., Anusha, N., Manimegalai, R. (2020). A Comprehensive Survey on Strategies in Multicore Architectures, Design Considerations and Challenges. In: Kumar, L., Jayashree, L., Manimegalai, R. (eds) Proceedings of International Conference on Artificial Intelligence, Smart Grid and Smart City Applications. AISGSC 2019 2019. Springer, Cham. https://doi.org/10.1007/978-3-030-24051-6_76

Download citation

  • DOI: https://doi.org/10.1007/978-3-030-24051-6_76

  • Published:

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-030-24050-9

  • Online ISBN: 978-3-030-24051-6

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics