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Analog IC Sizing Background

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Yield-Aware Analog IC Design and Optimization in Nanometer-scale Technologies

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Abstract

Analog designers often have to compromise on some circuit performances to achieve a handmade solution, due to the large number of constraints that must be fulfilled. This fact led to the appearance of several techniques and tools for the automation of analog IC sizing by both academy and industry. Despite the evolution of those techniques and tools, a substantial part of analog sizing tasks is still dependent on human intervention. Paradoxically, experience shows that once an EDA sizing tool finds a solution, a designer is able to improve that solution by adjusting one or a very small number of design parameters, and the paradox is that the designer was unable to achieve that original EDA optimal solution by himself, mainly due to the large number of constraints that must be satisfied. To understand how today’s EDA tools reach solutions and how a yield estimation technique can be embedded in those tools, this chapter presents information about the different techniques adopted in automatic analog IC sizing tools. Additionally, some background information about circuit parameters considered during the sizing process is also provided.

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Authors and Affiliations

  1. Instituto Superior Técnico, Instituto de Telecomunicações, Lisbon, Portugal

    António Manuel Lourenço Canelas & Nuno Cavaco Gomes Horta

  2. Instituto Politécnico de Tomar, Instituto de Telecomunicações, Lisbon, Portugal

    Jorge Manuel Correia Guilherme

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  1. António Manuel Lourenço Canelas
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Canelas, A.M.L., Guilherme, J.M.C., Horta, N.C.G. (2020). Analog IC Sizing Background. In: Yield-Aware Analog IC Design and Optimization in Nanometer-scale Technologies. Springer, Cham. https://doi.org/10.1007/978-3-030-41536-5_2

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