Abstract
Floorplanning is the art of any physical design. A well-thought-out floorplan leads to an ASIC design with higher performance and optimum area.
A designer has a duty to create timeless design. To be timeless you have to think really far into the future, not next year, not in two years but in 20 years minimum.
Philippe Starck
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Bibliography
N. Sherwani, Algorithms for VLSI Physical Design Automation, 2nd edn. (Kluwer Academic Publishers, Dordrecht, 1997)
K. Golshan, Physical Design Essentials, an ASIC Design Implementation Perspective (Springer Business Media, 2007) New York, USA
D. Chinnery, K. Keutzer, Closing the Power Gap between ASIC & Custom: Tools and Techniques for Low Power Design (Springer Science + Business Media, 2007) New York, USA
Cadence Design Systems, Inc., Rapid adoption kits based on a 10nm reference flow for new arm cortex (2016)
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Golshan, K. (2020). Floorplan and Timing. In: The Art of Timing Closure. Springer, Cham. https://doi.org/10.1007/978-3-030-49636-4_4
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DOI: https://doi.org/10.1007/978-3-030-49636-4_4
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