Skip to main content
SpringerLink
Log in

A Parallel and Distributed Topological Approach to 3D IC Optimal Layout Design

  • Conference paper
  • First Online:
Artificial Intelligence and Soft Computing (ICAISC 2020)

Part of the book series: Lecture Notes in Computer Science ((LNAI,volume 12415))

Included in the following conference series:

  • 1920 Accesses

Abstract

The task of 3D ICs layout design involves the assembly of millions of components taking into account many different requirements and constraints such as topological, wiring or manufacturability ones. It is a NP-hard problem that requires new non-deterministic and heuristic algorithms. Considering the time complexity, the commonly applied Fiduccia-Mattheyses partitioning algorithm is superior to any other local search method. Nevertheless, it can often miss to reach a quasi-optimal solution in 3D spaces. The presented approach uses an original 3D layout graph partitioning heuristics implemented with use of the extremal optimization method. The goal is to minimize the total wire-length in the chip. In order to improve the time complexity a parallel and distributed Java implementation is applied. Inside one Java Virtual Machine separate optimization algorithms are executed by independent threads. The work may also be shared among different machines by means of The Java Remote Method Invocation system.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 84.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 109.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. Ababei, C., et al.: Placement and routing in 3D integrated circuits. IEEE Des. Test 22(6), 520–531 (2005)

    Article  Google Scholar 

  2. Boettcher, S.: Extremal optimization: heuristics via coevolutionary avalanches. Comput. Sci. Eng. 2(6), 75–82 (2000)

    Article  Google Scholar 

  3. Coulouris, G., Dollimore, J., Kindberg, T., Blair, G.: Distributed Systems: Concepts and Design (5th Edition). Addison-Wesley, Boston (2011). ISBN 0-132-14301-1

    Google Scholar 

  4. Das, S., Chandrakasan, A., Reif, R.: Three-dimensional integrated circuits: performance, design methodology, and CAD tools. In: Proceedings of the IEEE Computer Society Annual Symposium on VLSI (2004)

    Google Scholar 

  5. De Micheli, G., Pavlidis, V., Atienza, V., Leblebici, Y.: Design methods and tools for 3D integration. In: Symposium on VLSI Tech Digest of Technical Papers, pp. 182–183 (2011)

    Google Scholar 

  6. Dong, X., Xie, Y.: System-level cost analysis and design exploration for three-dimensional integrated circuits (3D ICs). In: Proceedings of the 2009 Asia and South Pacific Design Automation Conference (ASP-DAC 2009). IEEE Press, Piscataway (2009)

    Google Scholar 

  7. Funke, J., Hougardy, S., Schneider, J.: Wirelength optimal rectangle packings. In: Proceedings of the Fourth International Workshop on Bin Packing and Placement Constraints, Nantes, France (2012)

    Google Scholar 

  8. Funke, J., Hougardy, S., Schneider, J.: An exact algorithm for wirelength optimal placements in VLSI design. VLSI J. 52, 355–366 (2016)

    Article  Google Scholar 

  9. Grzesiak-Kopeć, K., Ogorzałek, M.: 3D ICs layout hypergraph representation. Comput.-Aided Des. Appl. 12(4), 425–430 (2015)

    Article  Google Scholar 

  10. Grzesiak-Kopeć, K., Ogorzałek, M.: Extremal optimization approach to 3D design of integrated circuits layouts. In: The 7th International Conference on Advanced Computational Intelligence (ICACI) (2015b)

    Google Scholar 

  11. Grzesiak-Kopeć, K., Oramus, P., Ogorzałek, M.: Using shape grammars and extremal optimization in 3D IC layout design. Microelectron. Eng. 148, 80–84 (2015)

    Article  Google Scholar 

  12. Grzesiak-Kopeć, K., Oramus, P., Ogorzałek, M.: Hypergraphs and extremal optimization in 3D integrated circuit design automation. Adv. Eng. Inform. 33, 491–501 (2017)

    Article  Google Scholar 

  13. Hentschke, R.F.: Algorithms for wire length improvement of VLSI circuits with concern to critical paths. Ph.D thesis, Porto Alegre: PPGC da UFRGS (2007)

    Google Scholar 

  14. Kahng, A.B., Lienig, J., Markov, I.L., Hu, J.: VLSI Physical Design: From Graph Partitioning to Timing Closure. Springer, Netherlands (2011)

    Book  Google Scholar 

  15. Lengauer, T.: Combinatorial Algorithms for Integrated Circuit Layout. Wiley, Hoboken (1990)

    Book  Google Scholar 

  16. Li, Z., et al.: Hierarchical 3-D floorplanning algorithm for wirelength optimization. IEEE Trans. Circ. Syst. I: Regul. Papers 53(12), 2637–2646 (2006)

    Article  MathSciNet  Google Scholar 

  17. Liu, W., Nannarelli, A.: Net balanced floorplanning based on elastic energy model. In: NORCHIP, pp. 258–263 (2008)

    Google Scholar 

  18. MCNC: The MCNC set of benchmark circuits. http://lyle.smu.edu/~manikas/Benchmarks/MCNC_Benchmark_Netlists.html. Accessed 9 June 2015

  19. Mujtaba, H.: Hardware report: AMD naples high-performance server chips pack 32 cores, 64 threads – based on Zen with 8-channel memory, 128 PCIe lanes, launch in Q2 (2017). https://wccftech.com/amd-naples-server-chip-32-core-64-thread-preview. Accessed 10 March 2018

  20. Nain, R.-K., Chrzanowska-Jeske, M.: Fast placement-aware 3-D floorplanning using vertical constraints on sequence pairs. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 19(9), 1667–1680 (2011)

    Google Scholar 

  21. Xie, Y., Zhao, J.: Die-stacking Architecture, Die-stacking Architecture 1. Morgan and Claypool, San Rafael (2015)

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Department of Information Technologies, Jagiellonian University in Kraków, Kraków, Poland

    Katarzyna Grzesiak-Kopeć & Maciej Ogorzałek

Authors
  1. Katarzyna Grzesiak-Kopeć
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Maciej Ogorzałek
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Katarzyna Grzesiak-Kopeć .

Editor information

Editors and Affiliations

  1. Częstochowa University of Technology, Częstochowa, Poland

    Leszek Rutkowski

  2. Częstochowa University of Technology, Częstochowa, Poland

    Rafał Scherer

  3. Częstochowa University of Technology, Częstochowa, Poland

    Marcin Korytkowski

  4. Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada

    Witold Pedrycz

  5. AGH University of Science and Technology, Kraków, Poland

    Ryszard Tadeusiewicz

  6. Electrical and Computer Engineering, University of Louisville, Louisville, KY, USA

    Jacek M. Zurada

Rights and permissions

Reprints and permissions

Copyright information

© 2020 Springer Nature Switzerland AG

About this paper

Check for updates. Verify currency and authenticity via CrossMark

Cite this paper

Grzesiak-Kopeć, K., Ogorzałek, M. (2020). A Parallel and Distributed Topological Approach to 3D IC Optimal Layout Design. In: Rutkowski, L., Scherer, R., Korytkowski, M., Pedrycz, W., Tadeusiewicz, R., Zurada, J.M. (eds) Artificial Intelligence and Soft Computing. ICAISC 2020. Lecture Notes in Computer Science(), vol 12415. Springer, Cham. https://doi.org/10.1007/978-3-030-61401-0_62

Download citation

  • DOI: https://doi.org/10.1007/978-3-030-61401-0_62

  • Published:

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-030-61400-3

  • Online ISBN: 978-3-030-61401-0

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics

Search

Navigation