Architectures for Silicon-Based Implementation of m-D Discrete Hartley Transform Using Regularized Fast Hartley Transform

Abstract

This chapter introduces new architectures and solutions for the parallel computation of the m-D DHT – limited initially, for ease of illustration, to the 2-D case – and shown to be equally applicable, via the relationship of their kernels, to the computation of the m-D real-data DFT. The designs exploit the benefits of the regularized FHT, which has made it necessary to adopt: (1) a separable formulation of the DHT, the SDHT, so that the familiar Row-Column Method may be applied; and (2) memory partitioning, double-buffering, and parallel addressing schemes that are consistent with those used by the regularized FHT. Combining these features, the regularized FHT may be used for the processing of both the row-DHT and column-DHT stages of the 2-D formulation of the SDHT with the resulting parallel solutions possessing the same attractions as the regularized FHT – namely being resource-efficient, scalable and able to achieve a high computational density as space-complexity is traded off against time-complexity. Generalization of the designs to facilitate the processing of m-D data sets, for m ≥ 2, and the derivation of their associated space and time complexities and computational densities are also discussed in some detail as well as the constraints on their achieving and maintaining real-time operation. The chapter concludes with a discussion of the results obtained.