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Harnessing Voltage margins for Balanced Energy and Performance

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Computing at the EDGE

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Abstract

During chip fabrication, process variations can affect transistor dimensions (length, width, oxide thickness, etc. [1]), which have a direct impact on the threshold voltage of a MOS device [2]. As technology scales, the percentage of these variations compared to the overall transistor size increases and raises major concerns for designers, who aim to improve energy efficiency. Devices variation during fabrication known as static variation and remains constant during the chip lifetime. On top of that, transistor aging and dynamic variation in supply voltage and temperature, caused by different workload interactions, is also of primary importance. Both static and dynamic variations lead microprocessor architects to apply conservative guard bands (operating voltage and frequency settings) to avoid timing failures and guarantee correct operation, even in the worst-case conditions excited by unknown workloads or the operating environment [3, 4]. However, these guard bands impede the power consumption. To bridge the gap between energy efficiency and performance improvements, several hardware and software techniques have been proposed, such as Dynamic Voltage and Frequency Scaling (DVFS) [5]. The premise of DVFS is that the microprocessor’s workloads as well as the cores’ activity vary. Voltage and frequency-scaling during epochs where peak performance is not required enables a DVFS-capable system to achieve average energy-efficiency gains without affecting peak-performance adversely. However, energy-efficiency gains are limited by the pessimistic guard bands.

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Notes

  1. 1.

    The threshold voltage, commonly abbreviated as Vth, of a field-effect transistor (FET) is the minimum gate-to-source voltage VGS (th) that is needed to create a conducting path between the source and drain terminals. It is an important scaling factor to maintain power efficiency.

  2. 2.

    Our severity metric can be used above existing circuit-based techniques such as adaptive clocking. For instance, in the mechanism proposed in 0, adaptive-clocking can reduce the voltage at which SDCs occur. The frequency with which adaptation is deployed can be an input to our framework, thereby limiting the potential for performance degradation due to excessive deployment of adaptive-clocking induced frequency slowdown.

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Authors and Affiliations

  1. Department of Informatics and Telecommunications, National and Kapodistrian University of Athens, Athens, Greece

    George Papadimitriou & Dimitris Gizopoulos

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  1. George Papadimitriou
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  2. Dimitris Gizopoulos
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Correspondence to George Papadimitriou .

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  1. BELFAST, UK

    Georgios Karakonstantis

  2. Queen’s University Belfast, BELFAST, UK

    Charles J. Gillan

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Papadimitriou, G., Gizopoulos, D. (2022). Harnessing Voltage margins for Balanced Energy and Performance. In: Karakonstantis, G., Gillan, C.J. (eds) Computing at the EDGE. Springer, Cham. https://doi.org/10.1007/978-3-030-74536-3_3

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  • DOI: https://doi.org/10.1007/978-3-030-74536-3_3

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