Abstract
Passive is the threat when system confidentiality is at stake. Such threats do not cause direct damage by jeopardizing operations and generating erroneous results or causing stoppage of operations or even does not delay real time operations to cause a deadline miss. Hence, such threats are passive in nature. This involves leakage of secret information to adversaries [LJM13, GSC17a, GSC15]. For example, the secret key that is associated with cryptographic operations by a genuine user may be leaked to an adversary.
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References
J. Aarestad, D. Acharyya, R. Rad, J. Plusquellic, Detecting trojans through leakage current analysis using multiple supply pad\({I}_{\rm DDQ}\)s. IEEE Trans. Inf. Forensics Secur. 5(4), 893–904 (2010)
A. Askarov, D. Zhang, A.C. Myers, Predictive black-box mitigation of timing channels, in Proceedings of the 17th ACM Conference on Computer and Communications Security, CCS ’10 (2010), pp. 297–307
R.S. Chakraborty, S. Bhunia, Security against hardware trojan attacks using key-based design obfuscation. J. Electron. Test. 27(6), 767–785 (2011)
K. Guha, D. Saha, A. Chakrabarti, RTNA: securing SOC architectures from confidentiality attacks at runtime using ART1 neural networks, in 2015 19th International Symposium on VLSI Design and Test (2015), pp. 1–6
K. Guha, D. Saha, A. Chakrabarti, Real-time soc security against passive threats using crypsis behavior of geckos. J. Emerg. Technol. Comput. Syst. 13(3), 41:1–41:26 (2017)
K. Guha, D. Saha, A. Chakrabarti, Self aware SoC security to counteract delay inducing hardware trojans at runtime, in 2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID) (2017), pp. 417–422
K. Guha, S. Saha, A. Chakrabarti, Shirt (self healing intelligent real time) scheduling for secure embedded task processing, in 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID) (2018), pp. 463–464
K. Guha, D. Saha, A. Chakrabarti, Stigmergy-based security for SoC operations from runtime performance degradation of SoC components. ACM Trans. Embed. Comput. Syst. 18(2), 14:1–14:26 (2019)
A. Majumder, D. Saha, A. Chakrabarti, K. Guha, Dynamic power-aware scheduling of real-time tasks for FPGA-based cyber physical systems against power draining hardware trojan attacks. J. Supercomput. 76(11), 8972–9009 (2020)
K. Huang, Y. Liu, N. Korolija, J.M. Carulli, Y. Makris, Recycled IC detection based on statistical methods. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(6), 947–960 (2015)
D. Jayasinghe, A. Ignjatovic, S. Parameswaran, NORA: algorithmic balancing without pre-charge to thwart power analysis attacks, in 2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID) (2017), pp. 167–172
C. Liu, J. Jou, Efficient coverage analysis metric for HDL design validation. IEE Proc. Comput. Digit. Tech. 148(1), 1–6 (2001)
Y. Liu, Y. Jin, Y. Makris, Hardware trojans in wireless cryptographic ICs: silicon demonstration & detection method evaluation, in Proceedings of the International Conference on Computer-Aided Design, ICCAD ’13 (2013), pp. 399–404
C. Liu, J. Rajendran, C. Yang, R. Karri, Shielding heterogeneous MPSoCs from untrustworthy 3PIPs through security-driven task scheduling. IEEE Trans. Emerg. Top. Comput. 2(4), 461–472 (2014)
S. Mal-Sarkar, R. Karam, S. Narasimhan, A. Ghosh, A. Krishna, S. Bhunia, Design and validation for FPGA trust under hardware trojan attacks. IEEE Trans. Multi-Scale Comput. Syst. 2(3), 186–198 (2016)
S. Narasimhan, D. Du, R.S. Chakraborty, S. Paul, F.G. Wolff, C.A. Papachristou, K. Roy, S. Bhunia, Hardware trojan detection by multiple-parameter side-channel analysis. IEEE Trans. Comput. 62(11), 2183–2195 (2013)
Luis Ribeiro, Mats Björkman, Transitioning from standard automation solutions to cyber-physical production systems: an assessment of critical conceptual and technical challenges. IEEE Syst. J. 12(4), 3816–3827 (2018)
J.J. Rajendran, O. Sinanoglu, R. Karri, Building trustworthy systems using untrusted components: a high-level synthesis approach. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 24(9), 2946–2959 (2016)
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Guha, K., Saha, S., Chakrabarti, A. (2021). Bypassing Passive Attacks. In: Self Aware Security for Real Time Task Schedules in Reconfigurable Hardware Platforms. Springer, Cham. https://doi.org/10.1007/978-3-030-79701-0_5
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DOI: https://doi.org/10.1007/978-3-030-79701-0_5
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