Abstract
Active threats are associated with attacks that cause direct damage to a system, eventually jeopardizing it. This comprise either generation of erroneous results [MWP+09, GSC19a] or preventing result generation within deadline [GSC17, GSC19b]. The former is an attack to system integrity, while the latter is an issue related to system availability.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
H.A.M. Amin, Y. Alkabani, G.M.I. Selim, System-level protection and hardware Trojan detection using weighted voting. J. Adv. Res. 5(4), 499–505 (2014)
S. Bhunia, M.S. Hsiao, M. Banga, S. Narasimhan, Hardware trojan attacks: threat analysis and countermeasures. Proc. IEEE 102(8), 1229–1247 (2014)
C. Bolchini, A. Miele, Reliability-driven system-level synthesis for mixed-critical embedded systems. IEEE Trans. Comput. 62(12), 2489–2502 (2013)
S. Bhunia, M. Tehranipoor, Hardware Security—A Hands on Approach (Elsevier Morgan Kaufmann Publishers, 2018). ISBN: 9780128124772
M.-S. Bouguerra, D. Trystram, F. Wagner, Complexity analysis of checkpoint scheduling with variable costs. IEEE Trans. Comput. 62(6), 1269–1275 (2013)
K. Chatterjee, D. Das, Semiconductor manufacturers’ efforts to improve trust in the electronic part supply chain. IEEE Trans. Compon. Packag. Technol. 30(3), 547–549 (2007)
X. Cui, K. Ma, L. Shi, K. Wu, High-level synthesis for run-time hardware Trojan detection and recovery, in Proceedings of the 51st Annual Design Automation Conference, DAC ’14 (2014), pp. 157:1–157:6
U. Guin, D. DiMase, M. Tehranipoor, Counterfeit integrated circuits: detection, avoidance, and the challenges ahead. J. Electron. Test. 30(1), 9–23 (2014)
K. Guha, A. Majumder, D. Saha, A. Chakrabarti, Reliability driven mixed critical tasks processing on FPGAS against hardware Trojan attacks, in 21st Euromicro Conference on Digital System Design, DSD 2018, Prague, Czech Republic, August 29–31, 2018, ed. by M. Novotný, N. Konofaos, A. Skavhaug (IEEE Computer Society, 2018), pp. 537–544
K. Guha, A. Majumder, D. Saha, A. Chakrabarti, Criticality based reliability against hardware trojan attacks for processing of tasks on reconfigurable hardware. Microprocess. Microsyst. 71 (2019)
K. Guha, D. Saha, A. Chakrabarti, Self aware SoC security to counteract delay inducing hardware Trojans at runtime, in 2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID) (2017), pp. 417–422
K. Guha, S. Saha, A. Chakrabarti, Shirt (self healing intelligent real time) scheduling for secure embedded task processing, in 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID) (2018), pp. 463–464
K. Guha, D. Saha, A. Chakrabarti, SARP: self aware runtime protection against integrity attacks of hardware Trojans, in VLSI Design and Test, Singapore (2019), pp. 198–209
K. Guha, D. Saha, A. Chakrabarti, Stigmergy-based security for SoC operations from runtime performance degradation of SoC components. ACM Trans. Embed. Comput. Syst. 18(2), 14:1–14:26 (2019)
U. Guin, X. Zhang, D. Forte, M. Tehranipoor, Low-cost on-chip structures for combating die and IC recycling, in Proceedings of the 51st Annual Design Automation Conference, DAC ’14 (2014), pp. 87:1–87:6
T. Hayashi, A. Kojima, T. Miyazaki, N. Oda, K. Wakita, T. Furusawa, Application of FPGA to nuclear power plant I&C systems, in Progress of Nuclear Safety for Symbiosis and Sustainability (Springer, 2014), pp. 41–47
T.H. Kim, R. Persaud, C.H. Kim, Silicon odometer: an on-chip reliability monitor for measuring frequency degradation of digital circuits. IEEE J. Solid-State Circuits 43(4), 874–880 (2008)
C. Liu, J. Jou, Efficient coverage analysis metric for HDL design validation. IEE Proc. Comput. Digit. Tech. 148(1), 1–6 (2001)
C. Liu, J. Rajendran, C. Yang, R. Karri, Shielding heterogeneous MPSoCs from untrustworthy 3PIPs through security-driven task scheduling, in 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) (2013), pp. 101–106
C. Liu, J. Rajendran, C. Yang, R. Karri, Shielding heterogeneous MPSoCs from untrustworthy 3PIPs through security-driven task scheduling. IEEE Trans. Emerg. Top. Comput. 2(4), 461–472 (2014)
S. Mal-Sarkar, R. Karam, S. Narasimhan, A. Ghosh, A. Krishna, S. Bhunia, Design and validation for FPGA trust under hardware Trojan attacks. IEEE Trans. Multi-Scale Comput. Syst. 2(3), 186–198 (2016)
D. McIntyre, F. Wolff, C. Papachristou, S. Bhunia, D. Weyer, Dynamic evaluation of hardware trust, in 2009 IEEE International Workshop on Hardware-Oriented Security and Trust (2009), pp. 108–111
S. Narasimhan, D. Du, R.S. Chakraborty, S. Paul, F.G. Wolff, C.A. Papachristou, K. Roy, S. Bhunia, Hardware Trojan detection by multiple-parameter side-channel analysis. IEEE Trans. Comput. 62(11), 2183–2195 (2013)
J.J. Rajendran, O. Sinanoglu, R. Karri, Building trustworthy systems using untrusted components: a high-level synthesis approach. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 24(9), 2946–2959 (2016)
S. Sarma, N. Dutt, P. Gupta, N. Venkatasubramanian, A. Nicolau, Cyberphysical-system-on-chip (CPSoC): a self-aware MPSoC paradigm with cross-layer virtual sensing and actuation, in Proceedings of the 2015 Design, Automation, Test in Europe Conference & Exhibition, DATE ’15 (2015), pp. 625–628
M. Tehranipoor, F. Koushanfar, A survey of hardware Trojan taxonomy and detection. IEEE Des. Test Comput. 27(1), 10–25 (2010)
K. Xiao, D. Forte, M. Tehranipoor, A novel built-in self-authentication technique to prevent inserting hardware Trojans. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(12), 1778–1791 (2014)
K. Xiao, X. Zhang, M. Tehranipoor, A clock sweeping technique for detecting hardware Trojans impacting circuits delay. IEEE Des. Test 30(2), 26–34 (2013)
Y. Zheng, X. Wang, S. Bhunia, SACCI: scan-based characterization through clock phase sweep for counterfeit chip detection. IEEE Trans. VLSI Syst. 23(5), 831–841 (2015)
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
Copyright information
© 2021 The Author(s), under exclusive license to Springer Nature Switzerland AG
About this chapter
Cite this chapter
Guha, K., Saha, S., Chakrabarti, A. (2021). Counteracting Active Attacks. In: Self Aware Security for Real Time Task Schedules in Reconfigurable Hardware Platforms. Springer, Cham. https://doi.org/10.1007/978-3-030-79701-0_6
Download citation
DOI: https://doi.org/10.1007/978-3-030-79701-0_6
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-030-79700-3
Online ISBN: 978-3-030-79701-0
eBook Packages: Computer ScienceComputer Science (R0)