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Using Off-the-Shelf Hardware Transactional Memory to Implement Speculative While in OpenMP

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OpenMP in a Modern World: From Multi-device Support to Meta Programming (IWOMP 2022)

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Abstract

This paper presents Speculative While (SWh), a technique that enables Speculative Task Execution (STE) in OpenMP to accelerate while loops marked by the proposed while construct and the swh clause. With SWh, the speculative tasks are generated by the OpenMP task construct in while loops (from linear algebra or goal finding algorithms) where control dependencies between iterations can be speculated. This paper also presents a detailed analysis of the application of Hardware Transactional Memory (HTM) support to implement Speculative While and describes a preliminary evaluation of SWh implementation using HTM. As a result, it provides evidence to support the performance benefits of using STE over HTM to parallelize some well-known benchmarks. Experimental results reveal that by implementing SWh over HTM, speed-ups of up to 1.8\(\times \) can be obtained for the Gauss-Seidel benchmark.

This work is supported by the Sao Paulo Research Foundation (grants 18/07446-8, 20/01665-0, and 18/15519-5).

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Notes

  1. 1.

    This technique is called Scalar Expansion.

References

  1. Ayguade, E., et al.: The design of OpenMP tasks. IEEE Trans. Parallel Distrib. Syst. (TPDS) 20(3), 404–418 (2009)

    Article  Google Scholar 

  2. Azuelos, N., Etsion, Y., Keidar, I., Zaks, A., Ayguadé, E.: Introducing speculative optimizations in task dataflow with language extensions and runtime support. In: 2012 Data-Flow Execution Models for Extreme Scale Computing, pp. 44–47, September 2012

    Google Scholar 

  3. Damron, P., Fedorova, A., Lev, Y., Luchangco, V., Moir, M., Nussbaum, D.: Hybrid transactional memory. In: International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), San Jose, California, USA, pp. 336–346. ACM (2006)

    Google Scholar 

  4. Gayatri, R., Badia, R.M., Ayguade, E.: Loop level speculation in a task based programming model. In: 20th Annual International Conference on High Performance Computing, pp. 39–48 (2013)

    Google Scholar 

  5. Herlihy, M., Moss, J.E.: Transactional memory: architectural support for lock-free data structures. In: International Conference on Computer Architecture (ISCA), San Diego, CA, USA, pp. 289–300, May 1993

    Google Scholar 

  6. Intel Corporation: Intel architecture instruction set extensions programming reference. Chapter 8: Intel transactional synchronization extensions (2015)

    Google Scholar 

  7. Le, H., et al.: Transactional memory support in the IBM POWER8 processor. IBM J. Res. Dev. 59(1), 8:1–8:14 (2015)

    Google Scholar 

  8. Moore, K.E., Bobba, J., Moravan, M.J., Hill, M.D., Wood, D.A.: LogTM: Log-based transactional memory. In: High Performance Computer Architecture (HPCA), pp. 254–265 (2006)

    Google Scholar 

  9. OpenMP-ARB: OpenMP application program interface version 4.0 (2013)

    Google Scholar 

  10. OpenMP-ARB: OpenMP application program interface version 4.5 (2015)

    Google Scholar 

  11. OpenMP-ARB: OpenMP application program interface version 5.0 (2018)

    Google Scholar 

  12. Perez, J.M., Badia, R.M., Labarta, J.: A dependency-aware task-based programming environment for multi-core architectures. In: 2008 IEEE International Conference on Cluster Computing, Tsukuba, Japan, pp. 142–151 (2008)

    Google Scholar 

  13. Press, W.H., Teukolsky, S.A., Vetterling, W.T., Flannery, B.P.: Numerical Recipes 3rd Edition: The Art of Scientific Computing. Cambridge University Press, Cambridge (2007)

    MATH  Google Scholar 

  14. Rauchwerger, L., Padua, D.: Parallelizing while loops for multiprocessor systems. In: International Parallel Processing Symposium, pp. 347–356 (1995)

    Google Scholar 

  15. Salamanca, J., Amaral, J.N., Araujo, G.: Evaluating and improving thread-level speculation in hardware transactional memories. In: IEEE International Parallel and Distributed Processing Symposium (IPDPS), Chicago, USA, pp. 586–595 (2016)

    Google Scholar 

  16. Salamanca, J., Amaral, J.N., Araujo, G.: Using hardware-transactional-memory support to implement thread-level speculation. IEEE Trans. Parallel Distrib. Syst. 29(2), 466–480 (2018)

    Article  Google Scholar 

  17. Salamanca, J., Baldassin, A.: Evaluating the performance of speculative DOACROSS loop parallelization with taskloop. In: International Conference on High Performance Computing and Simulation (HPCS), Barcelona, Spain (2020)

    Google Scholar 

  18. Salamanca, J., Baldassin, A.: Using hardware transactional memory to implement speculative privatization in OpenMP. In: Chapman, B., Moreira, J. (eds.) LCPC 2020. LNTCS, vol. 13149, pp. 57–73. Springer, Cham (2020). https://doi.org/10.1007/978-3-030-95953-1_5

    Chapter  Google Scholar 

  19. Salamanca, J., Baldassin, A.: A proposal for supporting speculation in the OpenMP taskloop construct. In: Fan, X., de Supinski, B.R., Sinnen, O., Giacaman, N. (eds.) IWOMP 2019. LNCS, vol. 11718, pp. 246–261. Springer, Cham (2019). https://doi.org/10.1007/978-3-030-28596-8_17

    Chapter  Google Scholar 

  20. Salamanca, J., Baldassin, A.: Improving speculative taskloop in hardware transactional memory. In: McIntosh-Smith, S., de Supinski, B.R., Klinkenberg, J. (eds.) IWOMP 2021. LNCS, vol. 12870, pp. 3–17. Springer, Cham (2021). https://doi.org/10.1007/978-3-030-85262-7_1

    Chapter  Google Scholar 

  21. Shavit, N., Touitou, D.: Software transactional memory. Distrib. Comput. 10(2), 99–116 (1997). https://doi.org/10.1007/s004460050028

    Article  MATH  Google Scholar 

  22. Sohi, G.S., Breach, S.E., Vijaykumar, T.N.: Multiscalar processors. In: International Symposium on Computer Architecture (ISCA), S. Margherita Ligure, Italy, pp. 414–425 (1995)

    Google Scholar 

  23. Steffan, J., Mowry, T.: The potential for using thread-level data speculation to facilitate automatic parallelization. In: High-Performance Computer Architecture (HPCA), Washington, USA, pp. 2–13 (1998)

    Google Scholar 

  24. Steffan, J.G., Colohan, C.B., Zhai, A., Mowry, T.C.: A scalable approach to thread-level speculation. In: International Conference on Computer Architecture (ISCA), Vancouver, British Columbia, Canada, pp. 1–12 (2000)

    Google Scholar 

  25. The LLVM Project: LLVM 12.0.0 (2021). https://github.com/llvm/llvm-project

  26. Yoo, R.M., Hughes, C.J., Lai, K., Rajwar, R.: Performance evaluation of Intel transactional synchronization extensions for high-performance computing. In: International Conference on High Performance Computing, Networking, Storage and Analysis (SC), Denver, Colorado, pp. 19:1–19:11 (2013)

    Google Scholar 

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Acknowledgements

The authors would like to thank the anonymous reviewers for the insightful comments.

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Correspondence to Juan Salamanca .

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Salamanca, J., Baldassin, A. (2022). Using Off-the-Shelf Hardware Transactional Memory to Implement Speculative While in OpenMP. In: Klemm, M., de Supinski, B.R., Klinkenberg, J., Neth, B. (eds) OpenMP in a Modern World: From Multi-device Support to Meta Programming. IWOMP 2022. Lecture Notes in Computer Science, vol 13527. Springer, Cham. https://doi.org/10.1007/978-3-031-15922-0_4

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