Abstract
Phase Frequency Detector (PFD) being one of the important block of the high frequency clock generator encounters two major problems in its design. One being the dead zone and other is blind zone. The presence of the dead zone leads to phase noise. Blind zone increases the lock time of the clock generator. This paper presents a novel edge detector based PFD. In the proposed PFD, zero blind zone is achieved by eliminating the reset pulse beyond the dead zone region. The proposed PFD is designed in UMC 0.18 \(\upmu \)m CMOS process. It consumes power of 648 \(\upmu \)W at an operating frequency of 1 GHz. It is observed that the proposed PFD locks 43\(\%\) faster than the conventional PFD.
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Divya, M., Sundaram, K. (2022). A Novel Blind Zone Free, Low Power Phase Frequency Detector for Fast Locking of Charge Pump Phase Locked Loops. In: Arunachalam, V., Sivasankaran, K. (eds) Microelectronic Devices, Circuits and Systems. ICMDCS 2022. Communications in Computer and Information Science, vol 1743. Springer, Cham. https://doi.org/10.1007/978-3-031-23973-1_8
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DOI: https://doi.org/10.1007/978-3-031-23973-1_8
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