Abstract
Machine Learning (ML) is being widely used to enhance the performance and customize the service of different products and applications using actual operation data. Most ML-empowered systems are usually delivered as cloud solutions, which may represent different challenges specifically related to connectivity, privacy, security and stability. Different Implementation architectures of ML algorithms on edge and embedded devices have been explored in the literature. With respect to FPGAs, given that software functions can be implemented on the hardware logic fabric for acceleration purposes, synthesizing the hardware and configuring the implementation integration following changes in the ML models is a challenging task. In this paper we propose an adaptive architecture and flexible implementation model of Neural Networks (NN) on Xilinx FPGAs where changing the NN structure and/or size does not require a re-synthesis of the HW neither a reconfiguration of the system integration. Furthermore, we carried out a hardware optimization to enhance the performance of the IP acceleration cores and data transfer, and analyzed the underlying performance, accuracy and scalability for different NNs, up to 180000 parameters.
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Jakobsen, J., Jensen, M., Sharifirad, I., Boudjadar, J. (2023). A Flexible Implementation Model for Neural Networks on FPGAs. In: Abraham, A., Pllana, S., Casalino, G., Ma, K., Bajaj, A. (eds) Intelligent Systems Design and Applications. ISDA 2022. Lecture Notes in Networks and Systems, vol 716. Springer, Cham. https://doi.org/10.1007/978-3-031-35501-1_33
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DOI: https://doi.org/10.1007/978-3-031-35501-1_33
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