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3D Packaging Architectures and Assembly Process Design

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Book cover 3D Microelectronic Packaging

Part of the book series: Springer Series in Advanced Microelectronics ((MICROELECTR.,volume 57))

Abstract

In this chapter, the advantages and limitations of 3D architectures are discussed to provide context for why 3D stacking has become a key area of interest for product architects, why it has generated broad industry attention, and why its adoption has been tenous. The primary focus of this chapter is on 3D architectures that use Through Silicon Vias (TSVs), while other System In Package (SIP) architectures that do not rely on TSVs are discussed for completeness. The key elements of a TSV-based 3D architecture are described, followed by a description of the three methods of manufacturing wafers with TSVs (i.e., Via-First, Via-Middle, and Via-Last). An analysis of the different assembly process flows for 3D structures, broadly classified as (a) Wafer-to-Wafer (W2W), (b) Die-to-Wafer (D2W), and (c) Die-to-Die (D2D) assembly processes, is covered. Key design, assembly process, test process, and materials considerations for each of these flows are described. The chapter concludes with a discussion of current and anticipated challenges for 3D architectures.

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Notes

  1. 1.

    As a general definition, SIP refers to the on-package integration of multiple heterogeneous and/or homogenous ICs each of which may be in the form of unpackaged die, individually packaged die, or packaged modules. iNEMI (International Electronics Manufacturing Initiative) defines SIP as: System in Package is characterized by any combination of more than one active electronic component of different functionality plus optionally passives and other devices like MEMS or optical components assembled preferred into a single standard package that provides multiple functions associated with a system or subsystem. SIP is considered to be subset of the broader concept of System On Package (SOP) [4] where an entire computer system is built on a package.

  2. 2.

    An IP (Intellectual Property) block is reusable circuit block that performs a certain specialized functions and serves as a building block for constructing the SOC.

  3. 3.

    In most applications, Thermo-Compression Bonding (TCB) is used to create the fine pitch interconnect typically needed between two stacked die because of its superior alignment capability over reflow based flip-chip bonding [16].

  4. 4.

    WIO, i.e., Wide IO is a JEDEC standard memory, where the memory die are connected by TSVs [22].

  5. 5.

    Power efficiency quoted for the ESD case. See [Ref Hazkazemi paper] for a detailed review of power and performance differences between LPDDR and Wide-IO.

  6. 6.

    This is architecturally a more likely scenario for CPU-DRAM 3D stacks, since the CPU typically needs more bump interconnects than a DRAM and power delivery to a DRAM would require fewer TSVs compared to the converse case, where power is delivered to the CPU through the DRAM.

  7. 7.

    System cooling refers to the cooling solution attached to the SIP.

  8. 8.

    200 °C quoted as a typical lower temperature bound. A number of FEOL and MEOL processes have deposition temperatures significantly higher than 200 °C.

  9. 9.

    While this statement seems intuitively feasible, the authors are not aware of an authoritative study that establishes the design advantages of the Via First process over the Via Middle or Via Last options.

  10. 10.

    It should be pointed out that this model while illustrative is simplistic in a number of ways. In real life situations, the number of process steps is higher than n; individual process step yields vary and are not always independent of each other.

  11. 11.

    In industry parlance, the acronym KGD (Known Good Die) is used to describe the need for working pretested die.

  12. 12.

    Determining viability for assembly requires a careful optimization of cost (i.e., cost of probing die on a wafer needs to be balanced against the cost of package waste and need for additional test steps later in the flow) and test coverage (while checking a greater degree of die functionality before packaging is financially viable, it can also require more sophisticated Sort technology).

  13. 13.

    One of the key considerations in manufacturing costs is the time it takes to test units. The greater the amount of time, the lower the throughput and hence higher the costs. The goal in E-Test, Sort, and Package Level Test steps is to focus on test time minimization without impacting quality. Burn-In processes, on the other hand, are designed to run longer so that latent defects are screened out.

Abbreviations

2D:

Two dimensional

3D:

Three dimensional

BEOL:

Back end of line

BI:

Burn-In

CMP:

Chemical mechanical polishing

D2D:

Die-to-die

D2W:

Die-to-wafer

ECD:

Electro-chemical deposition

ECG:

Deleted in chapter

EMIB:

Embedded multi-die interconnect bridge

FEOL:

Front end of line

IP:

Intellectual property

KGD:

Known good die

KOZ:

Keep out zone

MCM:

Multi chip module

MCP:

Multi chip package

MEOL:

Middle end of line

MPM:

Multi package module

PECVD:

Plasma enhanced chemical vapor deposition

PVD:

Plasma vapor deposition

Rx:

Receiver

SBS:

Side by side

SIP:

System in package

SOC:

System on chip

TDP:

Thermal design power

TIM:

Thermal interface material

TSV:

Through silicon via

Tx:

Transmitter

W2W:

Wafer-to-wafer

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Acknowledgments

The authors would like to acknowledge Prismark Partners LLC, TechSearch International Inc, Shinko Electric Industries Co., Ltd, Amkor Technology®, ASE Group, SK Hynix, for their generous permission to use their pictures. Thanks are also due to Dr. Zhiguo Qian (Intel Corporation) for his help on the section on IO power dissipation, Upendra Sheth (Intel Corporation) for his help in compiling information on different MCP technologies, Dr. Arnab Choudhury (Intel Corporation) for help with thermal analysis and Prasad Ramanathan (Intel Corporation) for help with images. Guidance from Chris Nelson (Intel Corporation) on test processes is also gratefully acknowledged. Finally, thanks are due to Dheeraj Reddy (Intel Corporation) for a thorough review of this chapter.

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    Ravi Mahajan & Bob Sankman

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Mahajan, R., Sankman, B. (2017). 3D Packaging Architectures and Assembly Process Design. In: Li, Y., Goyal, D. (eds) 3D Microelectronic Packaging. Springer Series in Advanced Microelectronics, vol 57. Springer, Cham. https://doi.org/10.1007/978-3-319-44586-1_2

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