Abstract
In this paper, a novel redundant mechanism for dual port embedded SRAM is presented. This work relates to 1-D (one dimensional) bit oriented redundancy algorithm to increase the reliability and yield during manufacture of memory integrated circuit chips, specifically to the efficient use of the limited space available for fuse-activated redundant circuitry on such chips, and more particularly, to replace multiple faulty memory locations using one independent redundancy element per sub-array, and reducing the number of defects-signaling fuses. In this way we double the yield and repair rate with 0.5% area penalty.
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Srirama Murthy, G., Darvinder Singh, Sadulla Shaik (2016). An Area Efficient Built-In Redundancy Analysis for Embedded Memory with Selectable 1-D Redundancy . In: Corchado Rodriguez, J., Mitra, S., Thampi, S., El-Alfy, ES. (eds) Intelligent Systems Technologies and Applications 2016. ISTA 2016. Advances in Intelligent Systems and Computing, vol 530. Springer, Cham. https://doi.org/10.1007/978-3-319-47952-1_58
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DOI: https://doi.org/10.1007/978-3-319-47952-1_58
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