Abstract
In this chapter, we describe effective logic testing algorithms for relatively small (less than ten two-input NAND gate equivalent) hardware Trojan detection. Conventional post-manufacturing testing, test generation algorithms, and test coverage metrics cannot be readily extended to hardware Trojan detection. To reduce this lacuna, a novel test pattern generation technique termed multiple excitation of rare occurrence (MERO) is introduced, which maximizes the probability of inserted Trojans getting triggered and detected by logic testing, while drastically reducing the number of vectors compared to a weighted random pattern based test generation. Extending this approach and addressing some of the shortcomings of MERO, an enhanced automatic test pattern generation (ATPG) scheme using genetic algorithm and Boolean satisfiability is described and evaluated.
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References
S. Adee, The hunt for the kill switch. IEEE Spectr. 45(5), 34–39 (2008)
D. Agrawal, S. Baktir, D. Karakoyunlu, P. Rohatgi, B. Sunar, Trojan detection using IC fingerprinting, in SP’07: Proceedings of the IEEE Symposium on Security and Privacy (2007), pp. 296–310
M.E. Amyeen, S. Venkataraman, A. Ojha, S. Lee, Evaluation of the quality of N-detect scan ATPG patterns on a processor, in ITC’04: Proceedings of the International Test Conference (2004), pp. 669–678
M. Banga, M. Hsiao, A region based approach for the identification of hardware Trojans, in Proceedings of International Symposium on HOST (2008), pp. 40–47
M. Banga, M. Chandrasekar, L. Fang, M.S. Hsiao, Guided test generation for isolation and detection of embedded Trojans in ICs, in Proceedings of the 18th ACM Great Lakes symposium on VLSI (2008), pp. 363–366
R.S. Chakraborty, S. Bhunia, Security against hardware Trojan through a novel application of design obfuscation, in Proceedings of the 2009 International Conference on Computer-Aided Design (2009), pp. 113–116
R.S. Chakraborty, S. Narasimhan, S. Bhunia, Hardware Trojan: threats and emerging solutions, in Proceedings of IEEE International Workshop on HLDVT (2009), pp. 166–171
R.S. Chakraborty, F. Wolff, S. Paul, C. Papachristou, S. Bhunia, MERO: a statistical approach for hardware Trojan detection, in Cryptographic Hardware and Embedded Systems-CHES 2009 (2009), pp. 396–410
DARPA, TRUST in Integrated Circuits (TIC) – Proposer Information Pamphlet (2007). http://www.darpa.mil/MTO/solicitations/baa07-24/index.html
S. Dupuis, P.S. Ba, G. Di Natale, M.L. Flottes, B. Rouzeyre, A novel hardware logic encryption technique for thwarting illegal overproduction and Hardware Trojans, in 2014 IEEE 20th International On-Line Testing Symposium (IOLTS) (2014), pp. 49–54
S. Eggersglüß, R. Drechsler, High Quality Test Pattern Generation and Boolean Satisfiability (Springer, New York, 2012)
Z. Fu, Y. Marhajan, S. Malik, Zchaff sat solver (2004). Available: http://www.princeton.edu/chaff
M.J. Geuzebroek, J.T. van der Linden, A.J. van de Goor, Test point insertion that facilitates atpg in reducing test time and data volume, in Proceedings International Test Conference (2002), pp. 138–147
D.E. Goldberg, Genetic Algorithms in Search, Optimization and Machine Learning (Addison Wesley, Boston, 2006)
U. Guin, K. Huang, D. DiMase, J.M. Carulli, M. Tehranipoor, Y. Makris, Counterfeit integrated circuits: a rising threat in the global semiconductor supply chain. Proc. IEEE 102(8), 1207–1228 (2014)
Y. Huang, S. Bhunia, P. Mishra, Mers: statistical test generation for side-channel analysis based trojan detection, in Proceedings of the 2016 ACM SIGSAC Conference on Computer and Communications Security (2016), pp. 130–141
Y. Jin, Y. Makris, Hardware Trojan detection using path delay fingerprint, in IEEE International Workshop on Hardware-Oriented Security and Trust, HOST 2008 (2008), pp. 51–57
H.K. Lee, D.S. Ha, HOPE: an efficient parallel fault simulator for synchronous sequential circuits. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 15(9), 1048–1058 (1996)
B. Mathew, D.G. Saab, Combining multiple DFT schemes with test generation. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 18, 685–696 (2006)
X. Mingfu, H. Aiqun, L. Guyue, Detecting hardware Trojan through heuristic partition and activity driven test pattern generation, in Communications Security Conference (CSC), (2014), pp. 1–6
I. Pomeranz, S.M. Reddy, A measure of quality for n-detection test sets. IEEE Trans. Comput. 53(11), 1497–1503 (2004)
R.M. Rad, X. Wang, M. Tehranipoor, J. Plusquellic, Power supply signal calibration techniques for improving detection resolution to hardware trojans, in 2008 IEEE/ACM International Conference on Computer-Aided Design (2008), pp. 632–639
J. Rajendran, Y. Pino, O. Sinanoglu, R. Karri, Security analysis of logic obfuscation, in Proceedings of the 49th Annual Design Automation Conference (2012), pp. 83–89
E.M. Rudnick, J.H. Patel, G.S. Greenstein, T.M. Niermann, A genetic algorithm framework for test generation. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 16(9), 1034–1044 (1997)
S. Saha, R.S. Chakraborty, S.S. Nuthakki, Anshul, D. Mukhopadhyay, Improved test pattern generation for hardware Trojan detection using genetic algorithm and boolean satisfiability, in Proceedings of the 17th International Workshop on Cryptographic Hardware and Embedded Systems – CHES 2015, Saint-Malo, 13–16 Sept 2015, (2015), pp. 577–596
H. Salmani, M. Tehranipoor, J. Plusquellic, A layout-aware approach for improving localized switching to detect hardware Trojans in integrated circuits, in 2010 IEEE International Workshop on Information Forensics and Security (WIFS) (2010), pp. 1–6
H. Salmani, M. Tehranipoor, J. Plusquellic, A novel technique for improving hardware Trojan detection and reducing Trojan activation time. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 20(1), 112–125 (2012)
S.M.H. Shekarian, M.S. Zamani, S. Alami, Neutralizing a design-for-hardware-trust technique, in 2013 17th CSI International Symposium on Computer Architecture and Digital Systems (CADS) (2013), pp. 73–78
S. Wei, M. Potkonjak, Scalable hardware Trojan diagnosis. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 20(6), 1049–1057 (2012)
F. Wolff, C. Papachristou, S. Bhunia, R.S. Chakraborty, Towards Trojan-free trusted ICs: problem analysis and detection scheme, in DATE’08: Proceedings of the Conference on Design, Automation and Test in Europe (2008), pp. 1362–1365
X. Zhang, M. Tehranipoor, RON: an on-chip ring oscillator network for hardware Trojan detection, in Design, Automation & Test in Europe Conference & Exhibition (DATE) (2011), pp. 1–6
B. Zhou, W. Zhang, S. Thambipillai, J. Teo, A low cost acceleration method for hardware Trojan detection based on fan-out cone analysis, in Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis (2014), p. 28
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Govindan, V., Chakraborty, R.S. (2018). Logic Testing for Hardware Trojan Detection. In: Bhunia, S., Tehranipoor, M. (eds) The Hardware Trojan War. Springer, Cham. https://doi.org/10.1007/978-3-319-68511-3_7
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DOI: https://doi.org/10.1007/978-3-319-68511-3_7
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