Abstract
This chapter presents a multiport empirical model for I/O memory interface (e.g. inverter) designed based on fully depleted silicon on isolator (FDSOI) CMOS 28 nm process for signal and power integrity assessments. The analog mixed-signal identification signals that carry the information about I/O interface are recorded from large signal simulation setup. The model’s functions are extracted based on a nonlinear optimization algorithm and then implemented in Simulink software. The performance of the resulted model is validated in typical power and ground switching noise scenario. The developed empirical model accurately predicts the timing signal waveforms at the power, ground, and at the output port. Moreover, a comparative analysis between the artificial neural networks (ANNs) and adaptive neuro-fuzzy inference (ANFIS) models by exploring their modelling capabilities regarding the mathematical structures and identification algorithms in providing an accurate and computational effective behavioral model for the I/O buffers nonlinear dynamic behavior is investigated. The proposed model of the two-port I/O buffer is extracted from observable large-signal I/O current and voltages transient data. The training and computational performances along with the prediction accuracy of both modelling approaches are evaluated. The ANFIS model has better prediction accuracy by improving the normalized mean squared error (NMSE) by −13.5 dB while reducing by 11.66% the parameters’ number in cross-validation signal integrity scenario.
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Dghais, W., Chen, Y. (2018). Neuro-Fuzzy Nonlinear Dynamic Modelling for Signal Integrity Simulation. In: Alam, M., Dghais, W., Chen, Y. (eds) Real-Time Modelling and Processing for Communication Systems. Lecture Notes in Networks and Systems, vol 29. Springer, Cham. https://doi.org/10.1007/978-3-319-72215-3_4
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DOI: https://doi.org/10.1007/978-3-319-72215-3_4
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