Combined Modeling and Experimental Approach to Improve Mechanical Impact Survivability of GaN Power FET

Abstract

An alternative approach was taken to improve the high-g shock tolerance of electronic devices. Rather than stiffening electronic devices with potting, the electronic device mass was reduced by an appropriate amount to match the compliance of the device to the circuit board. The devices studied were field effect transistors (FET) in bare die form factor and allowed a wafer thinning process to be utilized. A global-local finite element model was utilized to determine the ideal die thickness for matching the compliance. Test boards were populated with optimal thinned devices and stock devices for comparison on the same board. A three step thinning process was utilized in an effort to minimize the induced defects from the thinning process. The circuit boards with mounted FET’s were dropped from a shock drop tower to successively higher g-shocks up to 60,000-g. The electrical performance of each device was tested and verified after each level of mechanical shock. In general, most devices (both stock and thin) fail electrically before visual evidence of mechanical failure was present. The highest peak acceleration a device survived without failure is used as a figure of merit (e.g. the device failed on the next higher drop). The average of the “peak survived accelerations” for thinned devices is found to be about 25% higher for thin devices than for stock devices. However there was a wide variability in the results, which appears to be the greatest challenge to improving stock tolerance predictability and high confidence reliability of electronic devices.