Abstract
This paper presents a communication network targeted for complex system-on-chip (SoC) and network-on-chip (NoC) designs. The Heterogeneous IP Block Interconnection v.2 (HIBI) aims at maximum efficiency and energy saving per transmitted bit combined with guaranteed quality-of-service (QoS) in transfers. Other features include support for arbitrary topologies with several clock domains, flexible scalablility in signalling and run-time reconfiguration of network parameters. HIBI has been implemented in VHDL and SystemC and synthesized in 0.18 CMOS technology with area comparable to other NoC wrappers. HIBI data transfers are shown to approach the maximum theoretical performance for protocol efficiency.
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Salminen, E., Lahtinen, V., Kangas, T., Riihimäki, J., Kuusilinna, K., Hämäläinen, T.D. (2004). HIBI v.2 Communication Network for System-on-Chip. In: Pimentel, A.D., Vassiliadis, S. (eds) Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2004. Lecture Notes in Computer Science, vol 3133. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-27776-7_43
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DOI: https://doi.org/10.1007/978-3-540-27776-7_43
Publisher Name: Springer, Berlin, Heidelberg
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