Abstract
The progressive CMOS scaling drives the success of the global semiconductor industry. Detailed knowledge of transistor behaviour is necessary to overcome the many fundamental challenges faced by chip and systems designers. Grid technology has enabled the constantly increasing statistical variability introduced by discreteness of charge and matter to be examined in unprecedented detail. Over 200,000 transistors subject to random discrete dopants variability have been simulated, the results of which provide detailed insight into underlying physical processes. This paper outlines recent scientific results of the nanoCMOS project, and describes the way in which the scientific goals have been reflected in the grid-based e-infrastructure.
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Asenov, A. et al. (2010). Enabling Cutting-Edge Semiconductor Simulation through Grid Technology. In: Lirkov, I., Margenov, S., Waśniewski, J. (eds) Large-Scale Scientific Computing. LSSC 2009. Lecture Notes in Computer Science, vol 5910. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-12535-5_43
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DOI: https://doi.org/10.1007/978-3-642-12535-5_43
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-12534-8
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