Abstract
The demand for power sensitive designs in system-on-chip (SoC) has grown significantly as MOSFET transistors scale down. Since portable battery powered devices such as cell phones, PDA’s, and portable computers are becoming more complex and prevalent, the demand for increased battery life will require designers to seek out new technologies and circuit techniques to maintain high performance and long operational lifetimes. As process dimensions shrink further toward nanometer technology, traditional methods of dynamic power reduction are becoming less effective due to the increased impact of standby power. Therefore, this paper proposes a novel adaptive power management system for nanoscale SoC design that reduces standby power dissipation. The proposed design method reduces the leakage power at least by 500 times for ISCAS’85 benchmark circuits designed using 32-nm CMOS technology comparing to the case where the method is not applied.
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References
Meijer, M., Pineda de Gyvez, J., Otten, R.: On-chip digital power supply control for system-on-chip applications. In: IEEE ISLPED, pp. 311–314 (August 2005)
Nakai, M., Akui, S., Seno, K., Meguro, T., Seki, T., Kondo, T., Hashiguchi, A., Kawahara, H., Kumano, K., Shimura, M.: Dynamic voltage and frequency management for a low-power embedded microprocessor. IEEE J. Solid-State Circuits 40(1), 28–35 (2005)
Wang, W., Mishra, P.: System-Wide Leakage-Aware Energy Minimization Using Dynamic Voltage Scaling and Cache Reconfiguration in Multitasking Systems. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 99, 1–9 (2011)
Nourivand, A., Al-Khalili, A.J., Savaria, Y.: Postsilicon Tuning of Standby Supply Voltage in SRAMs to Reduce Yield Losses Due to Parametric Data-Retention Failures. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 99, 1–13 (2011)
Pavan, T.K., Jagannadha Naidu, K., Shekar Babu, M.: Implementation of delay and power monitoring schemes to reduce the power consumption. In: IEEE International Conference on Signal Processing, Communication, Computing and Networking Technologies (ICSCCN), pp. 459–464 (July 2011)
Elgharbawy, W.M., Bayoumi, M.A.: Leakage sources and possible solutions in nanometer CMOS technologies. IEEE Circuits Syst. Magazine 5(4), 6–17 (2005)
Agarwal, A., Mukhopadhyay, S., Raychowdhury, A., Roy, K., Kim, C.H.: Leakage power analysis and reduction for nanoscale circuits. IEEE Micro. 26(2), 68–80 (2006)
Anis, M., Elmasry, M.: Multi-Threshold CMOS Digital Circuits: Managing Leakage Power. Kluwer, Norwell (2003)
Inukai, T., Hiramot, T., Sakurai, T.: Variable threshold voltage CMOS (VTCMOS) is series connected circuits. In: Int. Symp. Low Power Electron. Des. (ISLPED), pp. 201–206 (2001)
Roy, K., Mukhopadhyay, S., Mahmoodi-Meimand, H.: Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits. Proc. IEEE 91(2), 305–327 (2003)
Hokazono, A., Balasubramanian, S., Ishimaru, K., Ishiuchi, H., Liu, T.K., Hu, C.: MOSFET design for forward body biasing scheme. IEEE Electron Device Lett. 27(5), 387–389 (2006)
Kulkarni, M., Sheth, K., Agrawal, V.D.: Architectural power management for high leakage technologies. In: IEEE Southeastern Symposium on System Theory (SSST), pp. 67–72 (March 2011)
Ishibashi, K., Fujimoto, T., Yamashita, T., Okada, H., Arima, Y., Hashimoto, Y., Sakata, K., Minematsu, I., Itoh, Y., Toda, H., Ichihashi, M., Komatsu, Y., Hagiwara, M., Tsukada, T.: Low-voltage and low-power logic, memory, and analog circuit techniques for SoCs using 90 nm technology and beyond. IEICE Trans. Electon E89-C(3), 250–262 (2006)
Anis, M., Elmasry, M.: Multi-threhsold CMOS digital circuits. Kluwer Academic Publishers (2003)
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Ryu, JT., Kim, K.K. (2011). Adaptive Power Management for Nanoscale SoC Design. In: Kim, Th., et al. Communication and Networking. FGCN 2011. Communications in Computer and Information Science, vol 266. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-27201-1_49
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DOI: https://doi.org/10.1007/978-3-642-27201-1_49
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-27200-4
Online ISBN: 978-3-642-27201-1
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