Abstract
Very Large Scale Integration (VLSI) computing arrays for pattern recognition and image processing have received increasing attention in recent years. The computation speed of an array is often limited by the I/O bandwidth of the host system or the VLSI array. Reconfiguration techniques are used to restructure a computing array, so that successive functional computation steps can be carried out without the data leaving the array. Computation time is reduced, since with reconfiguration the limited I/O bandwidth affects only the first and last phases of the necessary computations.
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Young, T.Y., Liu, P.S. (1984). VLSI Arrays for Pattern Recognition and Image Processing: I/O Bandwidth Considerations. In: Fu, Ks. (eds) VLSI for Pattern Recognition and Image Processing. Springer Series in Information Sciences, vol 13. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-47523-8_3
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DOI: https://doi.org/10.1007/978-3-642-47523-8_3
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