Abstract
Programs for integrated circuit layout typically have two phases: placement and routing. The router should produce as efficient a layout as possible, but of course the quality of the routing depends heavily on the quality of the placement. On the other hand, the placement procedure would like to know how good a routing it can expect without actually routing the wires. This paper presents fast algorithms for optimal routing and for accurately estimating the area cost of such routings without actually laying them out.
The most common types of junctions occurring in layouts are T-shaped or X-shaped; this paper presents efficient algorithms to measure and produce the optimal rectilinear, two-layer routing in channels formed around such junctions. The ability to do this is based on the new notion of pairwise ordering which is used to propagate routing constraints from one part of a channel to the rest, and alleviates a fundamental problem plaguing traditional channel routers, in addition we present a greedy algorithm for optimal routing in rectangles with a new type of terminal ordering which comes up frequently in practice but has not been studied before.
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References
Dolev,D., Karplus,K., Siegel,A., Strong,A. amp; Ullman,J.D.: Optimal Wiring Between Rectangles; Proceedings of the Thirteenth Annual ACM Symposium on Theory of Computing, May 1981, pp. 312–317.
Goodhue,E : private communication (February 1981).
Hashimoto,A. amp; Stevens,J.: Wiring Routing by Optimizing Channel Assignment within Large Apertures; Proceedings of die Eighth Design Automation Workshop. IEEE, 1971, pp. 155–169.
Hightower,D.: The Interconnection Problem: A Tutorial; Computer, Vol 7, No. 4 (April 1974), pp. 18–32.
LaPaugh,A.S.: A Polynomial-time Algorithm for Optimal Routing Around a Rectangle; Proceedings of the Twenty-first Annual IEEE Symposium on Foundations of Computer Science, October 1980, pp. 282–293; also in Algorithms for Integrated Circuit Layout: An Analytic Approach, M1T/LCS/TR-248 (Ph.D. dissertation ), November 1980.
Leiserson, C.E.: Area-Efficient Graph Layouts (for VLSI); Proceedings of the Twenty-first Annual IEEE Symposium on Foundations of Computer Science, October 1980, pp. 270–281.
Mead,C. amp; Conway,L.: Introduction to VLSI Systems; Addison Wesley, Reading, Mass., 1980.
Preas,B.T.: Placement and Routing Algorithms for Hierarchical Integrated Circuit Layout; Computer Systems Laboratory Technical Report No. 180/SEL-79-032 (Ph.D. dissertation), Stanford University, August 1979.
Rivest,R.L.: The “PI” (Placement and Interconnect) System — Progress Report, unpublished manuscript, M.I.T, May 1981.
Thompson,C.D.: A Complexity Theory for VLSI; Technical Report CMU-CS-80-140 ( Ph.D. dissertation ), Carnegie-Mellon University, August 1980.
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© 1981 Carnegie-Mellon University
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Pinter, R.Y. (1981). Optimal Routing in Rectilinear Channels. In: Kung, H.T., Sproull, B., Steele, G. (eds) VLSI Systems and Computations. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-68402-9_19
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DOI: https://doi.org/10.1007/978-3-642-68402-9_19
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-68404-3
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