Abstract
VLSI structures and algorithms are given for bit-serial FIR filtering, IIR filtering, and convolution. We also present a bit-parallel FIR filter design. The structures are highly regular, programmable, and area-efficient. In fact, we will show that most are within log factors of asymptotic optimality. These structures are completely pipelined; that is, the throughput rate (bits/second) is independent of both word size and filter length. This is to be contrasted with algorithms designed and implemented in terms of, say, multipliers and adders whose throughput rates may depend on word length.
This work was supported I part by the National Science Foundation under Grant ECS-7916292, and in part by the U.S. Army Research Office, Durham, NC, under Grant DAAG29-79-C-0024.
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References
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© 1981 Carnegie-Mellon University
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Cappello, P.R., Steiglitz, K. (1981). Digital Signal Processing Applications of Systolic Algorithms. In: Kung, H.T., Sproull, B., Steele, G. (eds) VLSI Systems and Computations. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-68402-9_27
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DOI: https://doi.org/10.1007/978-3-642-68402-9_27
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