Abstract
This paper deals with the behavioral specification and description of digital circuits operating asynchronously. In particular, it is shown how the behavior of a composite circuit may be derived from the behavioral description of its components. The paper combines the theory of trace structures developed by M. Rem and J.L.A. van de Snepsheut with a suitable extension of the theory of marked graphs. It consequently achieves a considerable simplification of the way composite circuits are modeled and verified.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Berthelot, G., Roucairol, G. and Valk, R., “Reduction of Nets and Parallel programs”, Advanced Course on General Net Theory, w. Brauer, ed., LNCS 84, 1980.
Brzozowski, J.A., and Yoeli, M., “On a Ternary Model of Gate Networks”, IEEE Trans. Computers, C-28, March 1979, 178–184.
Brzozowski, J.A., and Yoeli, M., “Combinational Static CMOS Networks”, Research Report CS-85-42, Department of Computer Science, University of Waterloo, Ontario, Canada, December 1985.
De Cindio, F., De Michelis, G., Pomello, L. and Simone, C., “Equivalent Notions for Concurrent Systems”, Applications and Theory of Petri Nets, A. Pagnoni and G. Rozenberg, eds., Informatik-Fachberichte 66, Springer-Verlag, 1983.
Commoner, F., Holt, A.W., Even, S., and Pnueli, A., “Marked Directed Graphs”, J. Comp. and Syst. Sciences 5, 1971, 511–523.
Genrich, H., and Lautenbach, K., “Synchronizationsgraphen”, Acta Informatica 2, 1973, 143–161.
Hack, M., “Petri Net Languages”, Technical Report 159, Lab. for Computer Science, Mass. Inst. Tech., March 1976.
Hoare, C.A.R., Communicating Sequential Processes, Prentice Hall, 1985.
Lengauer, T., and Näher, S., “An Analysis of Ternary Simulation as a Tool for Race Detection in Digital MOS Circuits”, VLSI Algorithms and Architectures, International Workshop, Amalfi, Italy, 1984.
Milner, R., A Calculus of Communicating Systems, LNCS 92, 1980.
Petri, C.A., “Concurrency”, Advanced Course on General Net Theory, W. Brauer, ed., LNCS 84, 1980.
Peterson, J., Petri Net Theory and the Modeling of Systems, Prentice-Hall, 1981
Pehrson, B., and Yoeli, M., “A Communication System Net Model for Specification and Verification of Distributed Systems”, Proc. 4th Int. Conf. on Protocol Spec., Verif., and Testing, Skytop, 1984, North-Holland Publ.
Rem, M., “Partially Ordered Computations with Applications to VLSI Design”, Foundations of Computer Science IV, Pt.2, MC-Tract 159, 1–44, J.W. de Bakker, J. van Leeuwen, eds., Mathematical Center, Amsterdam, 1983.
Rozenberg, G., and Verraedt, R., “Subset Languages of Petri Nets, Part I”, Theor. Comp. Sci. 26, 1983, 301–326.
Seitz, C.L., “System Timing”, in: C. Mead and L. Conway, Introduction to VLSI Systems, 218–262, Addison-Wesley, 1980.
Van de Snepscheut, J.L.A., Trace Theory and VLSI Design, LNCS 200, 1985.
Yoeli, M., and Brzozowski, J.A., “A Mathematical Model of Digital CMOS Networks”, 1985 Canadian Conference on VLSI, Toronto, November 1985, 117–120.
Yoeli, M., and Etzion, T., “Behavioral Equivalence of Concurrent Systems”, Applications and Theory of Petri Nets, 292–305, A. Pagnoni and G. Rozenberg, eds., Informatik—Fachberichte 66, Springer-Verlag, 1983.
Yoeli, M., and Ginzburg, A., “Petri Net Languages and their Applications”, Research Report CS-78-45, Department of Computer Science, University of Waterloo, Ontario, Canada, November 1978.
Yoeli, M., “Synthesis of Concurrent Systems”, Application and Theory of Petri Nets, 183–186, C. Girault and W. Reisig, eds., Informatik-Fachberichte 52, Springer-Verlag, 1982.
Yoeli, M., “A Net Model of Communicating Systems”, Technical Report #372, Department of Computer Science, Technion-IIT, Haifa, Israel, July 1985.
Yoeli, M., and Pehrson, B., “Behavior-Preserving Reductions of Communicating System Nets”, Technical Report #1, Swedish Institute of Computer Science, Kista, Sweden, February 1986.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 1987 Springer-Verlag Berlin Heidelberg
About this chapter
Cite this chapter
Yoeli, M. (1987). Specification and Verification of Asynchronous Circuits Using Marked Graphs. In: Voss, K., Genrich, H.J., Rozenberg, G. (eds) Concurrency and Nets. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-72822-8_37
Download citation
DOI: https://doi.org/10.1007/978-3-642-72822-8_37
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-72824-2
Online ISBN: 978-3-642-72822-8
eBook Packages: Springer Book Archive