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Specification and Verification of Asynchronous Circuits Using Marked Graphs

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Concurrency and Nets

Abstract

This paper deals with the behavioral specification and description of digital circuits operating asynchronously. In particular, it is shown how the behavior of a composite circuit may be derived from the behavioral description of its components. The paper combines the theory of trace structures developed by M. Rem and J.L.A. van de Snepsheut with a suitable extension of the theory of marked graphs. It consequently achieves a considerable simplification of the way composite circuits are modeled and verified.

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© 1987 Springer-Verlag Berlin Heidelberg

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Yoeli, M. (1987). Specification and Verification of Asynchronous Circuits Using Marked Graphs. In: Voss, K., Genrich, H.J., Rozenberg, G. (eds) Concurrency and Nets. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-72822-8_37

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  • DOI: https://doi.org/10.1007/978-3-642-72822-8_37

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-72824-2

  • Online ISBN: 978-3-642-72822-8

  • eBook Packages: Springer Book Archive

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