Validation of a VLSI Chip Using Hierarchical Colored Petri Nets

Abstract

In this paper we focus on the task of modelling and validating the behavior of a VLSI chip using hierarchical Colored Petri Nets (CP-Nets or CPN’s). We discuss current practice in hardware design at the register transfer level. We describe an approach whereby engineering block diagrams, supplemented with suitable formal inscriptions, can be mapped directly to a CPN model. We show in detail a CPN model of an actual digital filter chip from a super-computer. We discuss the possibility of using this model to validate the logic of the design. We describe the potential of using formal analysis methods and propose a simplification technique for reducing the combinatorics involved in Occurrence Graph Analysis. We discuss performance issues and propose an extension to Colored Petri Nets that incorporates the concept of time.