Abstract
Reversible arithmetic units such as adders, subtractors and comparators form the essential components of any hardware implementation of quantum algorithms such as Shor’s factoring algorithm. Further, the synthesis methods proposed in the existing literature for reversible circuits target combinational and sequential circuits in general and are not suitable for synthesis of reversible arithmetic units. In this paper, we present several design methodologies for reversible subtractor and reversible adder-subtractor circuits, and a framework for synthesizing reversible arithmetic circuits. Three different design methodologies are proposed for the design of reversible ripple borrow subtractor that vary in terms of optimization of metrics such as ancilla inputs, garbage outputs, quantum cost and delay. The first approach follows the traditional ripple carry approach while the other two use the properties that the subtraction operation can be defined as \(a-b\) = \(\overline{\bar{a}+b}\) and \(a-b\) = \({a+\bar{b}+1}\), respectively. Next, we derive methodologies adapting the subtractor to also perform addition as selected with a control signal. Finally, a new synthesis framework for automatic generation of reversible arithmetic circuits optimizing the metrics of ancilla inputs, garbage outputs, quantum cost and the delay is presented that integrates the various methodologies described in our work.
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References
Al-Rabadi, A.N.: Closed-system quantum logic network implementation of the viterbi algorithm. Facta Universitatis-Ser.: Elec. Energ. 22(1), 1–33 (2009)
Babu, H.M., Chowdhury, A.: Design of a compact reversible binary coded decimal adder circuit. Elsevier J. Syst. Architect. 52, 272–282 (2006)
Biswas, A.K., Hasan, M.M., Chowdhury, A.R., Hasan Babu, H.M.: Efficient approaches for designing reversible binary coded decimal adders. Microelectron. J. 39(12), 1693–1703 (2008)
Bruce, J.W., Thornton, M.A., Shivakumaraiah, L., Kokate, P.S., Li, X.: Efficient adder circuits based on a conservative reversible logic gate. In: Proceedings of the IEEE Symposium on VLSI 2002, pp. 83–88 (2002)
Cheng, K.W., Tseng, C.C.: Quantum full adder and subtractor. Electron. Lett. 38(22), 1343–1344 (2002)
Choi, B.S., Van Meter, R.: On the effect of quantum interaction distance on quantum addition circuits. J. Emerg. Technol. Comput. Syst. 7, 11:1–11:17 (2011). http://doi.acm.org/10.1145/2000502.2000504
Chuang, M.L., Wang, C.Y.: Synthesis of reversible sequential elements. J. Emerg. Technol. Comput. Syst. 3(4), 1–19 (2008)
Cuccaro, S.A., Draper, T.G., Kutin, S.A., Moulton, D.P.: A new quantum ripple-carry addition circuit, October 2004. http://arXiv.org/quant-ph/0410184
Desoete, B., Vos, A.D.: A reversible carry-look-ahead adder using control gates. Integr. VLSI J. 33(1), 89–104 (2002)
Donald, J., Jha, N.K.: Reversible logic synthesis with fredkin and peres gates. J. Emerg. Technol. Comput. Syst. 4, 2:1–2:19 (2008)
Fredkin, E., Toffoli, T.: Conservative logic. Int. J. Theor Phys. 21, 219–253 (1982)
Golubitsky, O., Maslov, D.: A study of optimal 4-bit reversible toffoli circuits and their synthesis. IEEE Trans. Comput. 61(9), 1341–1353 (2012)
Gupta, P., Agarwal, A., Jha, N.K.: An algorithm for synthesis of reversible logic ciruits. IEEE Trans. Comput. Aided Des. 25(11), 2317–2330 (2006)
Yang, G., Song, X., Hung, W.N., Perkowski, M.: Bi-directional synthesis of 4-bit reversible circuits. Comput. J. 51(2), 207–215 (2008)
Thapliyal, H., Ranganathan, N.: Design of reversible sequential circuits optimizing quantum cost, delay and garbage outputs. ACM J. Emerg. Technol. Comput. Syst. 6(4), 14:1–14:35 (2010)
Haghparast, M., Jassbi, S., Navi, K., Hashemipour, O.: Design of a novel reversible multiplier circuit using HNG gate in nanotechnology. World App. Sci. J. 3(6), 974–978 (2008)
Hung, W.N., Song, X., Yang, G., Yang, J., Perkowski, M.: Optimal synthesis of multiple output boolean functions using a set of quantum gates by symbolic reachability analysis. IEEE Trans. Comput. Aided Des. 25(9), 1652–1663 (2006)
James, R.K., Jacob, K.P., Sasi, S.: Reversible binary coded decimal adders using toffoli gates. In: Ao, S.-L., Rieger, B., Chen, S.-S. (eds.) Advances in Computational Algorithms and Data Analysis. LNEE, vol. 15, pp. 117–131. Springer, Heidelberg (2008)
Khan, M.: Design of full-adder with reversible gates. In: Proceedings of the International Conference on Computer and Information Technology, pp. 515–519 (2002)
Kotiyal, S., Thapliyal, H., Ranganathan, N.: Reversible logic based multiplication computing unit using binary tree data structure. J. Supercomputing 71(7), 1–26 (2015)
Khan, M.H.A., Perkowski, M.A.: Quantum ternary parallel adder/subtractor with partially-look-ahead carry. J. Syst. Architect. 53(7), 453–464 (2007)
Maslov, D., Dueck, G.W.: Reversible cascades with minimal garbage. IEEE Trans. Comput. Aided Des. 23(11), 1497–1509 (2004)
Maslov, D., Dueck, G., Miller, D., Negrevergne, C.: Quantum circuit simplification and level compaction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(3), 436–444 (2008)
Maslov, D., Miller, D.M.: Comparison of the cost metrics for reversible and quantum logic synthesis (2006). http://arxiv.org/abs/quant-ph/0511008
Maslov, D., Saeedi, M.: Reversible circuit optimization via leaving the boolean domain. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(6), 806–816 (2011)
Matsunaga, T., Matsunaga, Y.: Customizable framework for arithmetic synthesis. In: Proceedings of the 12th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2004), Yokahama, pp. 315–318 (2004)
Meter, R., Munro, W., Nemoto, K., Itoh, K.M.: Arithmetic on a distributed-memory quantum multicomputer (2009). http://arxiv.org/abs/quant-ph/0607160
Mohammadi, M., Eshghi, M.: On figures of merit in reversible and quantum logic designs. Quantum Inf. Process. 8(4), 297–318 (2009)
Mohammadi, M., Eshghi, M., Haghparast, M., Bahrololoom, A.: Design and optimization of reversible BCD adder/subtractor circuit for quantum and nanotechnology based systems. World Appl. Sci. J. 4(6), 787–792 (2008)
Mohammadi, M., Haghparast, M., Eshghi, M., Navi, K.: Minimization optimization of reversible BCD-full adder/subtractor using genetic algorithm and don’t care concept. Int. J. Quantum Inf. 7(5), 969–989 (2009)
Murali, K.V.R.M., Sinha, N., Mahesh, T.S., Levitt, M.H., Ramanathan, K.V., Kumar, A.: Quantum information processing by nuclear magnetic resonance: experimental implementation of half-adder and subtractor operations using an oriented spin-7/2 system. Phys. Rev. A 66(2), 022313 (2002)
Nielsen, M.A., Chuang, I.L.: Quantum Computation and Quantum Information. Cambridge University Press, New York (2000)
Oliveira Jr., I., Sarthour, R., Bonagamba, T., Azevedo, E., Freitas, J.C.C.: NMR Quantum Information Processing. Elsevier Science, Amsterdam (2007)
Peres, A.: Reversible logic and quantum computers. Phys. Rev. A, Gen. Phys. 32(6), 3266–3276 (1985)
Prasad, A.K., Shende, V., Markov, I., Hayes, J., Patel, K.N.: Data structures and algorithms for simplifying reversible circuits. ACM JETC 2(4), 277–293 (2006)
Rice, J.E.: An introduction to reversible latches. Comput. J. 51(6), 700–709 (2008)
Saeedi, M., Zamani, M.S., Sedighi, M., Sasanian, Z.: Reversible circuit synthesis using a cycle-based approach. J. Emerg. Technol. Comput. Syst. 6, 131–1326 (2010)
Shende, V.V., Prasad, A., Markov, I., Hayes, J.: Synthesis of reversible logic circuits. IEEE Trans. CAD 22, 710–722 (2003)
Sastry, S.K., Shroff, H.S., Mahammad, S.N., Kamakoti, V.: Efficient building blocks for reversible sequential circuit design. In: Proceedings of the 49th IEEE International Midwest Symposium on Circuits and Systems, Puerto Rico, pp. 437–441, August 2006
Smolin, J.A., DiVincenzo, D.P.: Five two-bit quantum gates are sufficient to implement the quantum fredkin gate. Phys. Rev. A 53, 2855–2856 (1996)
Takahashi, Y.: Quantum arithmetic circuits: a survey. IEICE Trans. Fundam. E92–A(5), 1276–1283 (2010)
Takahashi, Y., Kunihiro, N.: A linear-size quantum circuit for addition with no ancillary qubits. Quantum Inf. Comput. 5(6), 440–448 (2005)
Takahashi, Y., Tani, S., Kunihiro, N.: Quantum addition circuits and unbounded fan-out, October 2009. http://arxiv.org/abs/0910.2530
Thapliyal, H., Ranganathan, N.: Design of efficient reversible binary subtractors based on a new reversible gate. In: Proceedings of the IEEE Computer Society Annual Symposium on VLSI, Tampa, Florida, pp. 229–234, May 2009
Thapliyal, H., Ranganathan, N.: Reversible logic-based concurrently testable latches for molecular QCA. IEEE Trans. Nanotechnol. 9(1), 62–69 (2010)
Thapliyal, H., Ranganathan, N., Ferreira, R.: Design of a comparator tree based on reversible logic. In: Proceedings of the 10th IEEE International Conference on Nanotechnology, Seoul, Korea, pp. 1113–1116, August 2010
Thapliyal, H., Ranganathan, N.: Design of efficient reversible logic-based binary and BCD adder circuits. ACM J. Emerg. Technol. Comput. Syst. (JETC) 9(3), 17 (2013)
Thomsen, M., Glück, R.: Optimized reversible binary-coded decimal adders. J. Syst. Archit. 54(7), 697–706 (2008)
Toffoli, T.: Reversible computing. Technical Report, Tech memo MIT/LCS/TM-151, MIT Lab for Computer Science (1980)
Trisetyarso, A., Meter, R.V.: Circuit design for a measurement-based quantum carry-lookahead adder (2009). http://arxiv.org/abs/0903.0748
Vedral, V., Barenco, A., Ekert, A.: Quantum networks for elementary arithmetic operations. Phys. Rev. A 54(1), 147–153 (1996)
Kotiyal, S., Thapliyal, H., Ranganathan, N.: Efficient reversible NOR gates and their mapping in optical computing domain. Microelectron. J. 6, 825–834 (2014)
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Thapliyal, H. (2016). Mapping of Subtractor and Adder-Subtractor Circuits on Reversible Quantum Gates. In: Gavrilova, M., Tan, C. (eds) Transactions on Computational Science XXVII. Lecture Notes in Computer Science(), vol 9570. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-662-50412-3_2
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