Abstract
There were no limits for speed of operation of arithmetic/logical circuits. One can always try to increase their speed. There were many proposed algorithms, which would work fast to specified arithmetic operations. So, there is the need for the implementation of a faster design by putting these fastest algorithms in a single ALU. The carry-select adder with K–S algorithm is found to be one of the fastest algorithms for addition and Urdhva-Tiryagbhyam Karastuba algorithm for multiplication, which are the most important operations in any central processing unit. We have used QUARTUS-II software. This design can be used where high speed computation is needed. This design would work for unsigned, fixed point, 8-bit operations. We have taken the different adder circuits and compared their performance. These circuits are the basic elements or building blocks of an ALU. The circuits have been simulated using 90 nm technology of Cadence and Quartus II EP2C20F484C7. Adders can be implemented using EX-OR/EX-XNOR gates, transmission gates, HSD (High Speed Domino) technique, domino logic. Parallel feedback carry adder, ripple carry adder, carry look ahead adder, carry-select adder are some of the adders that been implemented using Cadence and Quartus-II. We found that 10T PFCA is efficient compared to 11 T PFCA to some extent. Adders based on XOR and XNOR gates have the least delay compared to the other adders that we have used.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Shekhar S, Pandey, Bakshi A, Sharma V (2013) 128 Bit low power and area efficient carry select adder. Int J Comput Appl 69(6):0975–8887, May 2013
Chakali P, Patnala MK (2013) Design of high speed Kogge-Stone based carry select adder. Int J Emerg Sci Eng (IJESE) 1(4), Feb 2013. ISSN: 2319–6378
Dhanabal R, Bharathi V, Anand N, Joseph G, Oommen SS, Sahoo SK (2013) Comparison of existing multipliers and proposal of a new design for optimized performance. In: International journal of engineering and Technology (IJET), 2013
Premananda BS, Pai SS, Shashank B, Bhat SS (2013) Design and implementation of 8-bit vedic multiplier. Int J Adv Res Electri Electron Instrum Eng 2(12), Dec 2013
C Prema, CS Mainkanda Babu (2013) Enhanced high speed modular multiplier using Karatsuba algorithm. In: 2013 International Conference on Computer Communication and Informatics (ICCCI-2013), Jan 04–06, 2013, coimbatore, India
Dhanabal R, Bharathi V, Samhitha NR, Pavithra S, Prathiba S, Eugine J (2014) An efficient floating point multiplier design using combined booth and dadda algorithms. J Theor Appl Inf Technol 64(3):819824
Kukati S, Sujana DV, Udaykumar S, Jayakrishnan P, Dhanabal R (2013) Design and implementation of low power floating point arithmetic unit. In: Proceedings of the 2013 international conference on green computing, communication and conservation of energy, ICGCE 2013, art. no. 6823429, p. 205208, 2013
Dhanabal R, Ushashree (2013) Implementation of a high speed single precision floating point unit using verilog. Int J Comput Appl 0975–8887, 2013
Kogge PM, Stone HS (1973) A parallel algorithm for the efficient solution of a general class of re currence equations. In: IEEE transactions on computers, August 1973
Uma R, Vijayan V, Mohanapriya M, Paul S (2012) Area, delay and power comparison of adder topologies. Int J VLSI Des Commun Syst (VLSICS) 3:1 (February 2012)
P Annapurna Bai, M Vijaya Laxmi, Design of 128- bit Kogge-Stone low power parallel prefix VLSI adder for high speed arithmetic circuits. Int J Eng Adv Technol (IJEAT), ISSN: 2249–8958, 2:6, August 2013
JO Von Zur Gathenm, J Shokrollahi (2005) Efficient FPGA-based Karatsuba multipliers for polynomials over F2. In: B Preneel and Stafford Tavares (eds), Selected areas in cryptograp (sac 2005), No. 3897. Lecture notes in computer science. Springer, Kingston
Ratna Raju B, Satish DV (2013) A high speed 16*16 multiplier based on Urdhva Tiryakbhyam Sutra. Int J Sci Eng Adv Technol IJSEAT 1:5, Oct 2013
Dhanabal R, Bharathi V, Salim S, Thomas B, Soman H, Sahoo SK (2013) Design of 16-bit low power ALU—DBGPU. In: International journal of engineering and technology (IJET) 2013
Dhanabal R, Sahoo SK, Barathi V, Samhitha NR, Cherian NA, Jacob PM (2014) Implementation of floating point MAC using residue number system. J Theor Appl Inf Technol 62(2):458463
Dhanabal R, Bharathi V, Sri Chandrakiran G, Bharath Bhushan Reddy M (2014) VLSI design of floating point arithmetic and logic unit. J Theor Appl Inf Technol 64(3):703709
Dhanabal R, Srivastava D, Bharathi V (2014) Low power and area Efficient half adder based carry select adder design using common boolean logic for processing element. J Theor Appl Inf Technol 64(3):718723
Dhanabal R, Gunerkar R, Bharathi V (2014) Design and implementation of improved area efficient weighted modulo 2n + 1 adder design. ARPN J Eng Appl Sci 9(12):25692575
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2016 Springer India
About this paper
Cite this paper
Dhanabal, R., Sahoo, S.K., Bharathi, V., Devi, A., Sarma, R., Chowdary, D. (2016). Design of Basic Building Blocks of ALU. In: Suresh, L., Panigrahi, B. (eds) Proceedings of the International Conference on Soft Computing Systems. Advances in Intelligent Systems and Computing, vol 397. Springer, New Delhi. https://doi.org/10.1007/978-81-322-2671-0_30
Download citation
DOI: https://doi.org/10.1007/978-81-322-2671-0_30
Published:
Publisher Name: Springer, New Delhi
Print ISBN: 978-81-322-2669-7
Online ISBN: 978-81-322-2671-0
eBook Packages: EngineeringEngineering (R0)