Abstract
Two major trends in the VLSI chip design industry are the increase in system complexity and the increasing importance of short design times. The rise in chip complexity is motivated by consumer demand for higher performance products as well as increases in integration density which allow more functionality to be placed on a single chip. A consequence of this rise in complexity is an increasingly apparent chip validation bottleneck. Validation is a simulation intensive task and simulation time scales as the square of the increase in system complexity [9, 7]. Currently, complex VLSI chips take millions of hours of simulation to verify. Short design times are important because once a chip has been conceived there is a limited time window in which to bring the chip to market so that it will have competitive performance. For a new chip or system to be competitive when it reaches the marketplace, its performance must match the performance growth of the rest of the industry. This means that a complex chip that takes too long to design might miss its market window and by the time it reaches the market its performance will be uncompetitive. To reduce design time, system design bottlenecks need to be removed. System emulation and prototyping technology can play an important role in relieving the simulation bottleneck and managing system complexity.
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References
A. Agarwal, “Virtual Wires: A Technology for Massive Multi-FPGA Systems,” The Distinguished Lecture Series X, University Video Communications, December, 1994.
P. Athanas and H. Silvermann, “Processor Reconfiguration Through Instruction-Set Metamorphosis,” IEEE Computer, vol. 26, no. 3, pp. 11–18, March, 1993.
J. Babb, R. Tessier, and A. Agarwal, “Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators,” in IEEE Workshop on FPGA-based Custom Computing Machines, April, 1993.
P. Bertin, D. Roncin, and J. Vuilemin, “Introduction to Programmable Active Memories,” in Systolic Array Processors, J. McCanny et. al. editors, Prentice Hall, 1989.
P. Bertin, D. Roncin, and J. Vuilemin, “Programmable Active Memories: A Performance Assessment”, in Research on Integrated Systems, Proceedings of the 1993 Symposium, pp. 89–102, 1993.
S. D. Brown, R. J. Francis, J. Rose, Z. G. Vranesic, Field-Programmable Gate Arrays, MA: Kluwer Academic Publishers, 1992.
M. Butts, “Tutorial: FPGAs in Logic Emulation,” in Intl. Conf. on Computer Aided Design, November, 1993.
R. F. Cmelik and D. Keppel, “Shade: A Fast Instruction-Set Simulator for Execution Profiling”, University of Washington, Technical Report UWCSE 93–06-06, June 1993.
R. Collett, “Panel: Complex System Verification: The Challenge Ahead,” in Proceedings of the 31st IEEE/ACM Design Automation Conference, p. 320, San Diego, CA, June, 1994.
M. Dahl, J. Babb, R. Tessier, S. Hanono, D. Hoki, and A. Agarwal, “Emulation of the Sparcle Microprocessor with the MIT Virtual Wires Emulation System,” in IEEE Workshop on FPGA-based Custom Computing Machines, April, 1994.
G. DeMicheli, Synthesis and Optimization of Digital Circuits. New York, NY: McGraw-Hill, 1994.
G. DeMicheli, “Computer-Aided Hardware-Software Co-Design”, IEEE Micro, vol. 14, August, 1994.
R. French, M. Lam, J. Levitt, and K. Olukotun, “A General Method for Compiling Event-Driven Simulations”, in Proceedings of the 32nd ACM/IEEE Design Automation Conference, San Francisco, CA, June, 1995.
J. Gateley, et. al., “UltraSPARC-I Emulation”, in 32nd IEEE/ACM Design Automation Conference, San Francisco, CA, June, 1995.
J. Gateley and M. Blatt, “Reducing Time-to-Emulation through Flow Automation”, to appear in Nikkei Electronics, 1995.
S. Hauck, G. Boriello, C. Ebeling, “Mesh Routing Topologies for Multi-FPGA Systems,” in International Conference on Computer Design, pp. 170–177, 1994.
S. Hauck, G. Boriello, C. Ebeling, “Springbok: A Rapid-Prototyping System for Board-Level Designs,” in ACM/SIGDA 2nd International Workshop on Field- Programmable Gate Arrays, Berkeley, February, 1994.
J. L. Hennessy and D. A. Patterson, Computer Architecture A Quantitative Approach. San Mateo, California: Morgan Kaufman Publishers, Inc., 1990.
M. Horowitz and K. Keutzer, “Hardware-Software Co-Design,” in Synthesis and Simulation Meeting and International Interchange (SASIMI), pp. 5–14, Nara, Japan, Oct. 1993.
J. Kuskin, et. al, “The Stanford FLASH Multiprocessor”, in 21st Annual Int. Symp. Computer Architecture, pp. 302–313, Chicago, IL, May, 1994.
K. Olukotun, R. Helaihel, J. Levitt, and R. Ramirez, A Software/Hardware Cosyn- thesis Approach to Digital System Simulation,” IEEE Micro, vol. 14, August, 1994.
R. Razdan and M. Smith, “A High-Performance Microarchitecture with Hardware- Programmable Functional Units”, in Proceedings of the 21th Annual International Symposium on Microarchitecture, pp. 172–180, San Jose, CA, November, 1994.
R. L. Sites et. al., “Binary Translation”, Communications of the Association for Computing Machinery, vol. 36, no. 2, pp. 69–81, February, 1993.
M. D. Smith, “Tracing with Pixie”, Stanford University, Computer Systems Laboratory, Technical CSL-TR-91–497, Nov. 1991.
S. M. Trimberger, Field-Programmable Gate Array Technology, Boston, MA: Kluwer Academic Publishers, 1994.
Xilinx, Inc., The Programmable Logic Data Book, Xilinx, San Jose, 1994.
J. Varghese, M. Butts, J. Batcheller, “An Efficient Logic Emulation System.” IEEE Transactions on Very Large Scale Integration, vol. 1, no. 2, June 1993.
D. Van Den Bout, et. al., “AnyBoard: An FPGA-Based, Reconfigurable System,” in IEEE Design & Test of Computers, September, 1992.
S. Walters, “Computer-Aided Prototyping for ASIC-Based Systems,” IEEE Design & Test of Computers, June, 1991.
Zycad Corp., “Why the Paradigm RP Rapid Prototyping System is a Better Choice,” Zycad, Fremont, 1994.
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Helaihel, R., Olukotun, K. (1996). Emulation and Prototyping Of Digital Systems. In: De Micheli, G., Sami, M. (eds) Hardware/Software Co-Design. NATO ASI Series, vol 310. Springer, Dordrecht. https://doi.org/10.1007/978-94-009-0187-2_14
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DOI: https://doi.org/10.1007/978-94-009-0187-2_14
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