Abstract
Advances in integrated circuit technologies have made complementary MOS (CMOS) the preferred MOS technology for digital logic circuits. Cost effective design and fabrication of reliable CMOS VLSI chips require understanding of various CMOS technologies, logic families, failure modes, fault detection methods and design for testability methods. In this paper we will review some of the basic methods and issues related to the design and fault detection of CMOS logic circuits.
This work has been supported in part by SDIO/IST contract No. N00014-87-K-0419 managed by U.S. Office of Naval Research.
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© 1988 Kluwer Academic Publishers
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Reddy, S.M., Kundu, S. (1988). Fault Detection and Design For Testability of CMOS Logic Circuits. In: Lombardi, F., Sami, M. (eds) Testing and Diagnosis of VLSI and ULSI. NATO ASI Series, vol 151. Springer, Dordrecht. https://doi.org/10.1007/978-94-009-1417-9_4
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DOI: https://doi.org/10.1007/978-94-009-1417-9_4
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