Abstract
Much work has gone into automating the integrated circuit (IC) design process over the past few years (e.g. [1] [2] [3]). A variety of Computer-Aided Design (CAD) tools for the logic [4] [5] and physical design [6] of integrated circuits have been developed. It is clear that an integrated set of computer design aids coupled with an unified approach to data management is essential for VLSI design. To this end, research has focused on IC synthesis systems [7] i.e. systems which can automatically generate functionally correct mask-level layout of integrated circuit chips from high level, programming language-like specifications.
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© 1988 Kluwer Academic Publishers
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Devadas, S., Ma, HK.T., Sangiovanni-Vincentelli, A. (1988). Logic Verification, Testing and their Relationship to Logic Synthesis. In: Lombardi, F., Sami, M. (eds) Testing and Diagnosis of VLSI and ULSI. NATO ASI Series, vol 151. Springer, Dordrecht. https://doi.org/10.1007/978-94-009-1417-9_8
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DOI: https://doi.org/10.1007/978-94-009-1417-9_8
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