Abstract
Many experienced hand layout designers plan their layout by first rearranging the circuit topology in a way that they believe will result in the best final layout. The rearranged configuration is often drawn as a rough diagram indicating the desired placement of circuit elements and interconnection lines. Such a rough layout plan is then used as a guide during the tedious and error-prone actual layout process to remind the designer of the intended space utilization. In the past few years, layout plans of this type have become known as “stick diagrams” [1, 2] for they contain mostly simple line drawings.
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© 1984 Martinus Nijhoff Publishers, Dordrecht
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Hsueh, M.Y. (1984). Symbolic Layout Compaction. In: Antognetti, P., Pederson, D.O., de Man, H. (eds) Computer Design Aids for VLSI Circuits. NATO ASI Series, vol 48. Springer, Dordrecht. https://doi.org/10.1007/978-94-011-8006-1_11
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